Power-Efficient Application of Sleep Transistors to Enhance the Reliability of Integrated Circuits

Abstract

CMOS is furthermore the most widespread technology for digital designs as no feasible alternative is in sight to date and in the near future. The fundamental causes for this supremacy so far are the capability for miniaturization as well as the reliability and robustness of CMOS. Against the background of nanotechnology though, reliability concerns are arising with an alarming pace. The consequence is an increasing demand for approaches to improve both yield and lifetime reliability of today's complex integrated systems. Hence, a common solution is the redundant implementation of components. However, redundancy contradicts those other efforts in order to cope with power dissipation. Thus, the essential contribution of this work is an approach that increases the lifetime reliability of integrated circuits while delay and power penalties are kept to a minimum. Accordingly, "Sleep Transistors" (as a common technique to reduce standby leakage) are combined with the idea of modular redundancy. Furthermore, we propose an extended flow for the quantification of reliability on transistor level. Finally, the presented simulation results evidence that the suggested approach increases the lifetime reliability by more than a factor of two compared to initial designs.

Enhancement of System-Lifetime by Alternating Module Activation

“…It could be shown in previous works [7] that there is a moderate increase in dynamic power dissipation of ca. 6 %, while the leakage and area are roughly doubled.…”

“…The applied library consists of 8 standard cells described as VERILOG modules with a hard degradation limit that takes the cell active time into consideration. The levels of cell degradation are based on simulation results obtained from the test environment presented in [7]. Thereby, all cells were realized in a predictive 16 nm technology [18] and simulated with the same error models as in [7].…”

“…The levels of cell degradation are based on simulation results obtained from the test environment presented in [7]. Thereby, all cells were realized in a predictive 16 nm technology [18] and simulated with the same error models as in [7]. Next, all cells were simulated with different parameters for the error models, and with connected Sleep Transistors in on-and off-mode.…”