Power efficient CAM using adiabatic logic

Jothi, D.; Saranya, L.

doi:10.1109/iciiecs.2015.7193078

Cited by 3 publications

(3 citation statements)

References 6 publications

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“…The Complementary metal-Oxide-Semiconductor technology is common for large scale integration and low dissipation of power [6]. A novel CMOS logic for low power, which is based on the adiabatic switching principle, is called adiabatic logic.…”

Section: Introductionmentioning

confidence: 99%

Adiabatic Logic Based Energy Efficient Architecture of 1-Bit Magnitude Comparator for IOT Applications

Sanadhya¹,

Sanadhya²

2022

Journal of Internet Technology

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<p>The Internet of Things (IoT) applies the sensors and microcontrollers and links them through the internet. The eventual objective of low-power devices for Internet of Things is to lesser the overall system power and to extend battery life. For the development of energy efficient IoT devices, novel adiabatic techniques are proposed. By improving the performance of the comparator, one can improvise the whole system performance. The efficacy of computing devices depends on the performance of arithmetic circuits, including comparator. This paper proposes 1-bit comparator design using adiabatic techniques such as DC-DB PFAL (Direct current diode-based positive feedback adiabatic logic) and MPFAL (Modify positive feedback adiabatic logic) which are well-suited with an extensive range of applications (e.g. IoT sensors and an inbuilt analog to digital converter). For performance analysis, the results are compared together along with the other adiabatic and non adiabatic designs already reported in the literature. This paper proposes a way to decrease the dissipation of power and transistor count in binary circuits as it is one of the primary concerns. From the results, it is found that the design using DC-DB PFAL logic shows an improvement in power-delay-product of 69%, 94% and 90% compared to MPFAL, PFAL and ECRL techniques respectively.</p> <p> </p>

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Section: Introductionmentioning

confidence: 99%

Adiabatic Logic Based Energy Efficient Architecture of 1-Bit Magnitude Comparator for IOT Applications

Sanadhya¹,

Sanadhya²

2022

Journal of Internet Technology

View full text Add to dashboard Cite

show abstract

“…Though many low‐power techniques have been proposed to reduce power in ML and search line switching [5–8], the principle of adiabatic logic (AL) works well in the reduction of power dissipation by using the energy recovery process proposed in [9, 10]. The use of AL in the design of binary CAM cells [11–13] has resulted in better power savings. In this paper, the design and implementation of adiabatic TCAM core cells are proposed using efficient charge recovery logic (ECRL) for low‐power applications.…”

Section: Introductionmentioning

confidence: 99%

“…Many authors [9, 11–13, 30] have proved that ECRL is a better adiabatic circuit among the partial AL family because of their simplicity. Thus, the partial AL circuit using ECRL is explored for the analysis and design of QATCAM core cells.…”

Section: Introductionmentioning

confidence: 99%