Power Efficient Carry Propagate Adder

Kumre, Laxmi; Somkuwar, Ajay; Agnihotri, Ganga

doi:10.5121/vlsic.2013.4312

Cited by 6 publications

(5 citation statements)

References 13 publications

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“…Recent VLSI design, the occurrence of delays is predictable. Xilinx ISE is used for simulation and synthesis Delay of 13.88 ns [6] for a 16 bit Ling adder and 64 bit Sparse 2 adder has a delay of 35.026 ns [8].…”

Section: Discussionmentioning

confidence: 99%

FPGA Implementation of Area Efficient CMOS Multiplier using Fast Kogge Stone Look Ahead Logarithmic Adder

Malathi*,

Bharathi,

Jayanthi

2019

IJRTE

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Though Multipliers play a major role in all digital processing systems, still there is a research challenge related with area, delay, power, speed and accuracy parameters. Basically multipliers contains more number of adders (i.e.,) multiplication is done by repetitive additions. Highest care should be taken on adders. Partial Products (PP) part is middle process between multiplier, multiplicand and final addition. Next one about the methodology that Serial/parallel, Pipeline/parallel, Floating/decimal, Array, Binary/BCD, Fixed/Variable, Gate Level/Transistor Level. All the predecessors are having more controversy parameters. The forthcoming research concentrated on parallel, pipelining, decimal, binary and transistor level.

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Section: Discussionmentioning

confidence: 99%

FPGA Implementation of Area Efficient CMOS Multiplier using Fast Kogge Stone Look Ahead Logarithmic Adder

Malathi*,

Bharathi,

Jayanthi

2019

IJRTE

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“…An area efficient CLA is proposed by the authors in [7]. On the other hand, Carry Skip Adder(CSA) [8][9],carry increment adder (CIA) [6], [11]and carry select adder (CSLA) [10], [12]- [16] provides a good compromise in terms of area and delay, along with a simple and regular layout. Carry save adder have O(n) area and O(log n) delay.…”

Section: Related Workmentioning

confidence: 99%

Design and Implementation of an Improved Carry Increment Adder

Devi¹,

Kumar²,

Laishram³

2016

VLSICS

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A complex digital circuit comprises of adder as a basic unit. The performance of the circuit depends on the design of this basic adder unit. The speed of operation of a circuit is one of the important performance criteria of many digital circuits which ultimately depends on the delay of the basic adder unit. Many research works have been devoted in improving the delay of the adder circuit. In this paper we have proposed an improved carry increment adder (CIA) that improves the delay performance of the circuit. The improvement is achieved by incorporating carry look adder (CLA) in the design of CIA contrary to the previous design of CIA that employs ripple carry adder (RCA). A simulation study is carried out for comparative analysis. The coding is done in Verilog hardware description language (HDL) and the simulation is carried out in Xilinx ISE 13.1 environment.

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“…Generally only adder is used in ALU systems to realize other arithmetic logic like subtraction and multiplication etc [4]. In our proposed design the adder used is pipelined RCA (ripple carry adder) because of its compact design [10].…”

Section: Proposed Alu Designmentioning

confidence: 99%