Power‐efficient compensation circuit for fixed‐width multipliers

Abstract

A fixed-width multiplier receives two n-bit operands and generates an approximate n-bit product as the output. It truncates part of the partial products and employs an appropriate error compensation circuit in order to reduce the approximation error. In this study, a new error compensation circuit for the fixed-width multiplier has been proposed which utilises the correction vector (CV) and modified minor CV. The proposed error compensation circuit is capable of minimising both the mean error and the mean-square error. Post-synthesis results for 16-bit of fixed-width multiplier demonstrate that the proposed circuit has 3.50, 39.24, 42.91 and 44.91% reduced delay, area, power consumption and power-delay product when compared with the existing design reported in the literature.

Simple and hardware‐efficient row‐based direct‐mapping estimators in fixed‐width modified Booth multipliers

“…Recently, the great demand of high‐performance FWBM arises because of the wide applications of approximate computing (AC) 22,23 . Due to the huge amount of computation units, the area and power efficiency of FWBM have become the main concerns 24‐26 …”