Power-efficient decoder implementation based on state transparent convolutional codes

Abstract

In this study, a power-efficient very large-scale integration (VLSI) implementation for the convolutional code decoder is presented. Based on the state transparent convolutional code definition, the receiving codewords are classified into non-erroneous and erroneous segments separately. Different from the conventional Viterbi decoder (VD), the authors use a low-complexity decoder, denoted as bit reverse decoder, to recover the non-erroneous segments using reverse operation with a little power consumption and present the segment-based VD to decode the erroneous codeword segments. Then, the clock-gating technique is employed to switch between segment-based VD and bit reverse decoder for power saving. To further reduce the power consumption, the authors group registers into several segments in the survivor memory unit of the segment-based VD and also apply clock gating to each segment individually. According to the number of consecutive erroneous codeword segments, the corresponding numbers of register segments in the survivor memory unit are enabled and other register segments are clock-gated to reduce the switching activities. Besides, our design determines the start and terminal states of the survivor path to obtain correct results of erroneous segments without bit-error rate degradation. As compared with other decoders, our design requires less power without decreasing the decoding performance.

Multiscale unit‐memory convolutional codes

“…The second is a multiscale code with n = 2. This code has for G 1 , the Hamming parity generator matrix, and for G 2 , the best rate 2/4 UM code in [19], with generator polynomials F 0 = [1, 2, 3, 1] and F 1 = [1,3,3,2]. This code has d free = 6.…”

“…The fourth is a d free = 5 systematic, rate 4/8 UMC that does not have the multiscale structure (referred to as SYST). The generator polynomials for this code are F 0 = [1,2,4,8,6,3,4,12] and F 1 = [0,0,0,0, 9,14,11,7]. Fig.…”

“…This is owing to their byte-oriented structure, which can be matched to the alphabet of the outer code [2]. Partial UMCs have been designed in [3,4]. Lee [2] investigated the performance of a 2 m alphabet Reed-Solomon outer code with a memory m UM inner code to show the advantages.…”

VLSI Architecture for Configurable and Low-Complexity Design of Hard-Decision Viterbi Decoding Algorithm

“…Low-power issues are quite popular, hence many researches on this topic have been presented (e.g. [4][5][6][7][8]). Besides power consumption, researches have been done on speed performance [9] and area efficiency (e.g.…”

Performance Analysis of L2 and L5 CNAV Broadcast Ephemeris for Orbit Calculation

“…Although the Viterbi decoder can effectively correct transmitting errors, it is computationally demanding. A more efficient inner code decoding algorithm based on is implemented in this project. To illustrate how this decoder works, we first find the relationship between the inputs and outputs of the convolutional encoder.…”