Power efficient odd parity generator & checker circuits

Abstract

This paper presents three bit odd parity generator and detector circuits based on low power adiabatic logic technique. The paper proposes a new design approach which is being derived from CMOS. A simulative investigation on the proposed circuit has been carried out in NI Multisim at 0.5μm CMOS technology with L=0.5μm and W=1.25μm. The power consumption is compared with con ventional CMOS and two popular standard 2PASCL an d Adiabatic array logic technique which shows great improvement in power dissipations.

A power efficient fully adiabatic logic circuit design approach: application to inverter and 8421 to excess-3 code converter

“…C f 1 In the analysis, the capacitor value is maintained constant and fixed at pf 0.01 , although the frequency is varied. When the frequency of the supply voltage is higher, the reactance value of the capacitor is smaller, and the capacitor works as a good conductor.…”

“…In today's era, the widespread use of electronic gadgets such as mobile phones, laptops, pagers, and kindles, and the need to increase the devices speed for achieving greater performance, compelled designers to seek for energy efficient approach in VLSI circuit design process [1]. Therefore, decreasing power consumption in battery powered equipment is a crucial objective of low-power VLSI circuit design.…”