2022 5th International Conference on Contemporary Computing and Informatics (IC3I) 2022
DOI: 10.1109/ic3i56241.2022.10073148
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Power-Efficient Secured Hardware Design of AES Algorithm on High Performance FPGA

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Cited by 6 publications
(2 citation statements)
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“…In conjunction with our exploration of resource utilization, we meticulously monitored the power statistics during the execution of the ECC algorithm on the Kintex UltraScale+ 16nm FPGA. Our analysis yielded the following power consumption metrics: [7,10] • Total On-Chip Power: Recorded at 1.408 W, this metric represents the aggregate power consumption of the FPGA during the operation of the ECC algorithm. It works as a fundamental signal of the energy utilization profile within the device.…”
Section: B Total Power Consumptionmentioning
confidence: 99%
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“…In conjunction with our exploration of resource utilization, we meticulously monitored the power statistics during the execution of the ECC algorithm on the Kintex UltraScale+ 16nm FPGA. Our analysis yielded the following power consumption metrics: [7,10] • Total On-Chip Power: Recorded at 1.408 W, this metric represents the aggregate power consumption of the FPGA during the operation of the ECC algorithm. It works as a fundamental signal of the energy utilization profile within the device.…”
Section: B Total Power Consumptionmentioning
confidence: 99%
“…General Applications: 3DES is employed in legacy sys- General Applications: Quantum-safe cryptography emerges as a forward-looking area of research, ensuring security in a post-quantum computing era. [2,10]. "…”
mentioning
confidence: 99%