Power efficient structure for conversion between arbitrary sampling rates

Babić, Djordje; Renfors, Markku

doi:10.1109/lsp.2004.838193

Cited by 32 publications

(15 citation statements)

References 8 publications

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“…All the results have been obtained using Agilent's Advanced Design System (ADS) software. 3. Experimental results and discussion…”

Section: Methodsmentioning

confidence: 99%

“…The digital up-converter (DUC) provides interpolation, ltering, frequency translation, and summing of DUC channel outputs to produce digital IF outputs DUCs can be found in wireless base-station transmit electronics, specialized digital IF receive-test equipment, cable TV modulators, and software dened transmit-radio equipment. Test equipment and digital radio electronics typically use DUC devices combined with ADC and DAC to provide digital radio sections, or other specic applications such as receiver/ transmitter test equipment [3,4]. Interpolation of a signal by an integer up-sample factor can be accomplished by processing the signal, x[n], with the cascade of an expander and low-pass lter, as * corresponding author; e-mail: rajeevratan@aol.in shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

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Performance Comparison of QPSK Based Single and Double Stage Digital Interpolators

2013

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In this paper, the performance of single stage and double stage digital interpolators has been compared and has been showed that by using multi stage interpolation system the reliability of any communication system increases drastically. Digital signal interpolation systems can be implemented in a variety of ways. The basic interpolator for up-sampling can be a combination of an expander unit with an interpolation low-pass lter in cascade. Complicated implementations can be done by connecting multiple expander and low-pass lter pairs in cascade. This paper presents the ecient implementation of digital interpolation systems for up-sampling of single stage and double stage digital interpolators by using quadrature phase shift keying technique. Comparison is done in terms of spectrum of generated signal, envelope power, modulated signal trajectory, input and output constellation and noise performance.

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“…All the results have been obtained using Agilent's Advanced Design System (ADS) software. 3. Experimental results and discussion…”

Section: Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Performance Comparison of QPSK Based Single and Double Stage Digital Interpolators

2013

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“…Since the first polynomial interpolation structures proposed by Farrow in 1988 [1], the past decades have seen the arrival of numerous SRC architectures suitable for SDR that are amenable to an FPGA implementation. These may be grouped into four classes: Farrow structures-based architectures [2,3]; Cascaded IntegratorComb, or CIC-based [4][5][6][7][8][9]; polyphase FIR filters-based [10][11][12][13]; and hybrid methods [14][15][16]. Table 1 summarizes the methods listed above with their characteristics.…”

Section: Related Workmentioning

confidence: 99%

A Practical FPGA-Based Architecture for Arbitrary-Ratio Sample Rate Conversion

Tietche

Romain

Denby

2013

J Sign Process Syst

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Many digital systems for telecommunications are implemented via the Software Defined Radio technique today. In such systems, digitally implemented modules to interface analog-to-digital converters with the rest of the system working at a different clock rate can be required. When implementing these modules, generated spurious harmonics and limited hardware resource problems can be critical factors in embedded applications. The article describes a Field-Programmable Gate Array (FPGA) circuit for arbitrary-ratio re-sampling of signals in the Low Frequency to Very High Frequency bands, intended for Software Defined Radio applications. The proposed resampler allows to control Spurious Free Dynamic Range while providing a simple, practical interface between the input and output clock domains that requires no additional clock, thus making it appropriate for FPGA clock-limited designs. Both upsampling and down-sampling variants are presented. Resource utilization for FPGA implementations is also discussed.

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“…International Journal of Electronics filtering, mixing and complex to real conversion for the analogue IF output. The high-quality clock source provides sample timing to the DAC and a digital clock to the DUC (Babic, Vesma and Renfors 2001;Babic and Renfors 2005). The analogue IF output from the DAC is filtered and amplified.…”

Section: Interpolators Implementationmentioning

confidence: 99%

Performance comparison of quadrature amplitude modulation (QAM)-based single- and double-stage digital interpolators

Ratan

Sharma

Kohli

2013

International Journal of Electronics

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In this article, the performance of quadrature amplitude modulation (QAM)-based single-and double-stage digital interpolators have been compared. The basic interpolator for up-sampling can be a combination of an expander unit with an interpolation lowpass filter in cascade. Complicated implementations can be done by connecting multiple expander and low-pass filter pairs in cascade. This article presents the efficient and effective implementation of digital interpolation systems for up-sampling of single-and double-stage digital interpolators. Comparison is done in terms of spectrum of generated signal, envelope power, modulated signal trajectory, input and output constellation and noise performance. In this article, the proposed interpolation filters have been simulated in Agilent's Advanced Design System (ADS).

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Power efficient structure for conversion between arbitrary sampling rates

Cited by 32 publications

References 8 publications

Performance Comparison of QPSK Based Single and Double Stage Digital Interpolators

Performance Comparison of QPSK Based Single and Double Stage Digital Interpolators

A Practical FPGA-Based Architecture for Arbitrary-Ratio Sample Rate Conversion

Performance comparison of quadrature amplitude modulation (QAM)-based single- and double-stage digital interpolators

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