Power estimation technique for Reed-Muller logic circuits

Abstract

A power estimation technique for Reed-Muller logic circuits is proposed. Given the probability and transition density of input signals, AND/XOR gates are decomposed into a 2-input gate tree and its switching activity is calculated to estimate the power dissipation. Experimental results indicate that this proposed approach can well predict power dissipation of Reed-Muller logic without detail process information., denotes the output signal probability 1-4244-1132-7/07/$25.00