Power exploration for data dominated video applications

Wuytack, Sven; Catthoor, Francky; Nachtergaele, Lode; Man, H. De

doi:10.1109/lpe.1996.547539

Cited by 62 publications

(33 citation statements)

References 18 publications

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“…Later work by Cao et al [6] extends this optimization to consider data width scaling. Wuytack et al [16] have developed techniques to optimize the entire memory hierarchy of an application for power consumption based on application information. These previous approaches rely on application trace information to perform memory partitioning.…”

Section: Related Workmentioning

confidence: 99%

Power-aware RAM mapping for FPGA embedded memory blocks

Tessier¹,

Betz²,

Neto³

et al. 2006

Proceedings of the 2006 ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays

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Embedded memory blocks are important resources in contemporary FPGA devices. When targeting FPGAs, application designers often specify high-level memory functions which exhibit a range of sizes and control structures. These logical memories must be mapped to FPGA embedded memory resources such that physical design objectives are met. In this work a set of power-aware logical-to-physical RAM mapping algorithms are described which convert user-defined memory specifications to on-chip FPGA memory block resources. These algorithms minimize RAM dynamic power by evaluating a range of possible embedded memory block mappings and selecting the most power-efficient choice. Our automated approach has been integrated into a commercial FPGA compiler and tested with 40 large FPGA benchmarks. Through experimentation, we show that, on average, embedded memory dynamic power can be reduced by 21% and overall core dynamic power can be reduced by 7% with a minimal loss (1%) in design performance.

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Section: Related Workmentioning

confidence: 99%

Power-aware RAM mapping for FPGA embedded memory blocks

Tessier¹,

Betz²,

Neto³

et al. 2006

Proceedings of the 2006 ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays

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show abstract

“…Researchers in [4] introduced a C code transformation approach to make better use of address calculation units. Address generation has been shown to account for a large percent of energy dissipation in [3] and researchers have studied instruction-level power models [5].…”

Section: Problem Description and Related Workmentioning

confidence: 99%

DSP address optimization using a minimum cost circulation technique

Gebotys

1997

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ICCAD-97

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“…Consequently, reducing power consumption in portable devices has become a dominant design concern. Memory subsystems have been demonstrated to consume 50%-75% power budget of the entire system [1], [2]. As a consequence, memory hierarchies are being constructed to reduce the energy dissipation of the memory subsystem.…”

Section: Introductionmentioning

confidence: 99%

Overlay techniques for scratchpad memories in low power embedded processors

Verma

Marwedel

2006

IEEE Trans. VLSI Syst.

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Abstract-Energy consumption is one of the important parameters to be optimized during the design of portable embedded systems. Thus, most of the contemporary portable devices feature low-power processors coupled with on-chip memories (e.g., caches, scratchpads). Scratchpads are better than traditional caches in terms of power, performance, area, and predictability. However, unlike caches they depend upon software allocation techniques for their utilization. In this paper, we present scratchpad overlay techniques which analyze the application and insert instructions to dynamically copy both variables and code segments onto the scratchpad at runtime. We demonstrate that the problem of overlaying scratchpad is an extension of the Global Register Allocation problem. We present optimal and near-optimal approaches for solving the scratchpad overlay problem. The near-optimal scratchpad overlay approach achieves close to the optimal results and is significantly faster than the optimal approach. Our approaches improve upon the previously known static allocation technique for assigning both variables and code segments onto the scratchpad. The evaluation of the approaches for ARM7 processor reports, average energy, and execution time reductions of 26% and 14% over the static approach, respectively. Additional experiments comparing the overlayed scratchpads against unified caches of the same size, report average energy, and execution time savings of 20% and 10%, respectively. We also report data memory energy reductions of 45%-57% due to the insertion of a 1024-bytes scratchpad memory in the memory hierarchy of a digital signal processor (DSP).Index Terms-Code overlay, memory aware code optimization, scratchpad memory (SPM).

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Power exploration for data dominated video applications

Abstract: In this paper

Cited by 62 publications

References 18 publications

Power-aware RAM mapping for FPGA embedded memory blocks

Power-aware RAM mapping for FPGA embedded memory blocks

DSP address optimization using a minimum cost circulation technique

Overlay techniques for scratchpad memories in low power embedded processors

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