Power integrity improvement by controlling on-die PDN properties

Abstract

Power integrity has became a serious issue in the advanced CMOS digital systems, because power supply noise must be suppressed to guarantee normal logic operation and its stability. Therefore, chip-package-board co-design has become important by taking into consideration the total impedance seen from the chip. Especially, parallel resonance peaks in the distribution network (PDN) due to the chip-package interaction induces the unwanted power supply fluctuation, and results in the degradation of signal integrity and electromagnetic interference (EMI).In this paper, three test chips were designed with different onchip PDN properties. The effects of critical damping condition for the total PDN impedance on power supply noise has been examined by adding different RC circuit to the intrinsic on-die RC circuit of chip. The measurement and analysis of power supply noises for the three test chips showed typical characteristics of oscillatory region and damped regions The critical damping condition against the anti-resonance peak has been proved to be effective to suppress the power supply noise on the chip.