Power Management Using Test-Pattern Ordering for Wafer-Level Test During Burn-In

Bahukudumbi, S.; Chakrabarty, Krishnendu

doi:10.1109/tvlsi.2008.2006679

Cited by 7 publications

(11 citation statements)

References 35 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Testing during the burn-in process is a common practice since it reduces test and burn-in costs [Bahukud08a,Bahukud08b,Bahukud09]. However, power variations caused by scan-based testing may lead to large temperature fluctuations.…”

Section: Test Reorderingmentioning

confidence: 99%

“…This affects the accuracy of the burn-in process since the actual temperatures are not exactly known. Reducing power variations in order to reduce the temperature variations during burn-in is investigated in [Bahukud08a,Bahukud08b,Bahukud09]. The variation is reduced through test reordering.…”

Section: Test Reorderingmentioning

confidence: 99%

“…An efficient transition counting method is proposed to rapidly estimate the test power values. Then, a heuristic-based test-pattern ordering technique is proposed to minimize the fluctuations in the power dissipation during test [Bahukud08a,Bahukud08b,Bahukud09].…”

Section: Test Reorderingmentioning

confidence: 99%

See 2 more Smart Citations

Thermal Issues in Testing of Advanced Systems on Chip

Ghaleshahi¹

2015

View full text Add to dashboard Cite

Many cutting-edge computer and electronic products are powered by advanced Systems-on-Chip (SoC). Advanced SoCs encompass superb performance together with large number of functions. This is achieved by efficient integration of huge number of transistors. Such very large scale integration is enabled by a core-based design paradigm as well as deepsubmicron and 3D-stacked-IC technologies. These technologies are susceptible to reliability and testing complications caused by thermal issues. Three crucial thermal issues related to temperature variations, temperature gradients, and temperature cycling are addressed in this thesis.Existing test scheduling techniques rely on temperature simulations to generate schedules that meet thermal constraints such as overheating prevention. The difference between the simulated temperatures and the actual temperatures is called temperature error. This error, for past technologies, is negligible. However, advanced SoCs experience large errors due to large process variations. Such large errors have costly consequences, such as overheating, and must be taken care of. This thesis presents an adaptive approach to generate test schedules that handle such temperature errors.Advanced SoCs manufactured as 3D-stacked-ICs experience large temperature gradients. Temperature gradients accelerate certain early-life defect mechanisms. These mechanisms can be accelerated using gradientbased, burn-in like operations so that the defects are detected before shipping. Moreover, temperature gradients exacerbate some delay-related defects. In order to detect such defects, testing must be performed when appropriate temperature-gradients are enforced. Schedule-based techniques that enforces the temperature-gradients for burn-in like operations and delay testing are proposed in this thesis. Abstract iiThe last thermal issue addressed by this thesis is related to temperature cycling. Temperature cycling test procedures are usually applied to safetycritical systems to detect cycling-related early-life failures. Such failures affect advanced SoCs, particularly through-silicon-via structures in 3D-stacked-ICs. An efficient schedule-based cycling-test technique that combines cycling acceleration with testing is proposed in this thesis. The proposed technique fits into existing 3D testing procedures and does not require temperature chambers. Therefore, the overall cycling acceleration and testing cost can be drastically reduced.All the proposed techniques have been implemented and evaluated with extensive experiments based on ITC'02 benchmarks as well as a number of 3D stacked ICs. Experiments show that the proposed techniques work effectively and reduce the test costs. We have also developed a fast temperature simulation technique based on a closed-form solution for the temperature equations. Experiments demonstrate that the proposed simulation technique reduces the test schedule generation time by more than half.iii Populärvetenskaplig sammanfattningMånga banbrytande dator-och elektronikprodukter drivs...

show abstract

Section: Test Reorderingmentioning

confidence: 99%

Section: Test Reorderingmentioning

confidence: 99%

See 1 more Smart Citation

Thermal Issues in Testing of Advanced Systems on Chip

Ghaleshahi¹

2015

View full text Add to dashboard Cite

show abstract

“…Plenty of schemes have been proposed to reduce test power, such as low-power test scheduling [3], [4], test-pattern ordering [5], low-power test data compression [6], [7], scan chain structural conversion [8], low-power automatic test pattern generation (ATPG) algorithm [9], [10] and low-power Xfilling [11], [12] and so on. These schemes can reduce test power effectively, nevertheless some of them may result in poor test quality and the increase in test data.…”

Section: Introductionmentioning

confidence: 99%

Reseeding-Oriented Test Power Reduction for Linear-Decompression-Based Test Compression Architectures

Tian

Shen

et al. 2016

IEICE Trans. Inf. & Syst.

View full text Add to dashboard Cite

SUMMARYLinear feedback shift register (LFSR) reseeding is an effective method for test data reduction. However, the test patterns generated by LFSR reseeding generally have high toggle rate and thus cause high test power. Therefore, it is feasible to fill X bits in deterministic test cubes with 0 or 1 properly before encoding the seed to reduce toggle rate. However, Xfilling will increase the number of specified bits, thus increase the difficulty of seed encoding, what's more, the size of LFSR will increase as well. This paper presents a test frame which takes into consideration both compression ratio and power consumption simultaneously. In the first stage, the proposed reseeding-oriented X-filling proceeds for shift power (shift filling) and capture power (capture filling) reduction. Then, encode the filled test cubes using the proposed Compatible Block Code (CBC). The CBC can X-ize specified bits, namely turning specified bits into X bits, and can resolve the conflict between low-power filling and seed encoding. Experiments performed on ISCAS'89 benchmark circuits show that our scheme attains a compression ratio of 94.1% and reduces capture power by at least 15% and scan-in power by more than 79.5%.

show abstract

“…Reducing power variations in order to reduce the temperature variations during burn-in is discussed in [16], [17]. The variation is reduced through test reordering.…”

mentioning

confidence: 99%

A Test-Ordering Based Temperature-Cycling Acceleration Technique for 3D Stacked ICs

2015

View full text Add to dashboard Cite

In a modern three-dimensional integrated circuit (3D IC), vertically stacked dies are interconnected using through silicon vias. 3D ICs are subject to undesirable temperature-cycling phenomena such as through silicon via protrusion as well as void formation and growth. These cycling effects that occur during early life result in opens, resistive opens, and stress induced carrier mobility reduction. Consequently these early-life failures lead to products that fail shortly after the start of their use. Artificially-accelerated temperature cycling, before the manufacturing test, helps to detect such early-life failures that are otherwise undetectable. A test-ordering based temperaturecycling acceleration technique is introduced in this paper that integrates a temperature-cycling acceleration procedure with pre-, mid-, and post-bond tests for 3D ICs. Moreover, it reduces the need for costly temperature chamber based temperature-cycling acceleration methods. All these result in a reduction in the overall test costs. The proposed method is a test-ordering and schedule based solution that enforces the required temperature cycling effect and simultaneously performs the tests whenever appropriate. Experimental results demonstrate the efficiency of the proposed technique.

show abstract

Power Management Using Test-Pattern Ordering for Wafer-Level Test During Burn-In

Cited by 7 publications

References 35 publications

Thermal Issues in Testing of Advanced Systems on Chip

Thermal Issues in Testing of Advanced Systems on Chip

Reseeding-Oriented Test Power Reduction for Linear-Decompression-Based Test Compression Architectures

A Test-Ordering Based Temperature-Cycling Acceleration Technique for 3D Stacked ICs

Contact Info

Product

Resources

About