Power minimisation techniques at the RT-level and below

Abstract

A dichotomy exists in the design of modern microelectronic systems: they must be low power and high performance, simultaneously. This dichotomy largely arises from the use of these systems in battery-operated portable (wearable) platforms. Accordingly, the goal of low-power design for battery-powered electronics is to extend the battery service life while meeting performance requirements. Unless optimisations are applied at different levels, the capabilities of future portable systems will be severely limited by the weight of the batteries required for an acceptable duration of service. In fixed, power-rich platforms, the packaging cost and power density/reliability issues associated with high power and high performance systems also force designers to look for ways to reduce power consumption. Thus, reducing power dissipation is a design goal even for non-portable devices since excessive power dissipation results in increased packaging and cooling costs as well as potential reliability problems. Meanwhile, following Moore's Law, integrated circuit densities and operating speeds have continued to go up in unabated fashion. The result is that chips are becoming larger, faster and more complex and because of this, consuming increasing amounts of power.These increases in power pose new and difficult challenges for integrated circuit designers. While the initial response to increasing levels of power consumption was to reduce the supply voltage, it quickly became apparent that this approach was insufficient. Designers subsequently began to focus on advanced design tools and methodologies to address the myriad of power issues. Complicating designers' attempts to deal with these issues are the complexities -logical,

Reducing jitter in embedded systems employing a time-triggered software architecture and dynamic voltage scaling

“…This clock-gating technique (Abdollahi and Pedram, 2006) has been applied in a novel processor, PowerPro architecture (Programmable Power M anagement Architecture) which supports dynamic adjustments o f the active datapath width (Ishihara and Yasuura, 1998b). The processor obtains a PADWC (Programmable Active Datapath Width Control) function which provides the instruc tions that specify operation and control the variable datapath width.…”

“…This approach can be implemented by using sleep transistors (one PMOS and one NMOS) in series with the transistors o f each logic block, to make a virtual power supply and ground: this provides a "power gate" for reducing power in idle mode (Abdollahi and Pedram, 2006 Partitioning techniques enable parts o f a device to be associated with a particular clock domain (Butts and Sohi, 2000). This allows functional units which do not require a high clock speed to be implemented separately, to save leakage power.…”

“…It would be straightforward to ensure that the supply voltage was set to the lowest level after entering the idle mode, in order to reduce the leakage power (see Equation 2.8). Such techniques could be compared with power gating (Abdollahi and Pedram, 2006), as discussed in Section 2.3.4.…”