Power optimization and stage op-amp linearity relaxation in pipeline ADCs with digital comparator offset calibration

Ginés, Antonio; Peralías, E.; Aledo, Cristina; Rueda, A.

doi:10.1109/dcis.2014.7035572

Cited by 1 publication

(2 citation statements)

References 9 publications

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“…Moreover, increasing the control resolution from 6 bits in [14] to 8 bits in [15], while using equivalent 0.18 µm complementary MOS (CMOS) technologies and minimal device sizing, has reduced the comparison speed to more than 75%. In [12], an advanced search algorithm was also presented. This algorithm has been used to control a 4 bit offset calibration scheme leading to achieve almost ideal resolution.…”

Section: Introductionmentioning

confidence: 99%

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Design optimisation procedure for digital mismatch compensation in latch comparators

Khanfir

Mouine²

2018

IET Circuits, Devices & Systems

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Digital calibration schemes generally allow for high-speed operation and reduced power consumption at the price of lower accuracy compared with their analogue counterparts. However, in dynamic comparators, when exceeding 4 or 5 bits, any resolution increase will be progressively traded against the circuit parameters. This study presents a three-step design procedure to optimise the comparator performance for a given N. First, a new configuration of the latch comparator has allowed optimising the comparison speed in terms of N. Second, the calibration scheme has been reduced to a simple digital sequencer to perform a progressive capacitive offset trimming. Third, the sequencer automatic increment has been programmed to stop at optimal operation to achieve the best calibration accuracy. The proposed method has then been applied to design a latch comparator with 7 bit calibration control in a commercially available 0.18 µm complementary metal-oxide-semiconductor technology. Post-layout statistical simulations have shown that the circuit can achieve up to 5.9 bit calibration resolution without altering the comparator performances.

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Section: Introductionmentioning

confidence: 99%

“…Despite the correction granularity, the digital offset calibration is a practical solution in terms of the operation speed [11], power consumption [12] and design time and effort compared with full custom implementations [10]. This is mainly true when the target calibration resolution is <4 or 5 bits [13].…”

Section: Introductionmentioning

confidence: 99%

Design optimisation procedure for digital mismatch compensation in latch comparators

Khanfir

Mouine²

2018

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

show abstract

Power optimization and stage op-amp linearity relaxation in pipeline ADCs with digital comparator offset calibration

Cited by 1 publication

References 9 publications

Design optimisation procedure for digital mismatch compensation in latch comparators

Design optimisation procedure for digital mismatch compensation in latch comparators

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