Power optimization for VLSI circuits and systems

Zhao, Peiyi; Wang, Zhongfeng; Hang, Guoqiang

doi:10.1109/icsict.2010.5667299

Cited by 11 publications

(4 citation statements)

References 23 publications

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“…Merging of clock buffers reduces the gate capacitance. As the activity factor of a free clock net is 1, reducing a small amount of capacitance will translates to considerable amount of reduction in dynamic power [11] .…”

Section: A Clock Buffer Mergingmentioning

confidence: 99%

Power Optimization Techniques for High Speed Processor Core in Sub 14nm Technology Node

Mounica¹,

Svnit²,

Shah³

2017

IJVSP

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Optimization of power can be done at different levels of abstraction e.g., system level, RTL level, Circuit level, Layout level. With continuous scaling of the technology node optimization of power and overall power management on SoC are the key challenges in addition to meeting the performance requirements. This paper gives an idea of various techniques at circuit level to reduce power consumption without affecting the performance of the chip.

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Section: A Clock Buffer Mergingmentioning

confidence: 99%

Power Optimization Techniques for High Speed Processor Core in Sub 14nm Technology Node

Mounica¹,

Svnit²,

Shah³

2017

IJVSP

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show abstract

“…Design contains DFF to control the conveyance of the neighborhood clock signal "CLK "to the memory, and the "Lock signals along the way passing the worldwide clock source to the nearby clock signal are dynamic [10]. The yield of DFF and worldwide clock feeds to AND based RTL circuit, which produce neighborhood clock signal for memory [11]. Power utilization is drastically expanding for SRAM-FPGAs, thusly lower power FPGA hardware and new CAD devices are required.…”

Section: Introductionmentioning

confidence: 99%

Enhanced Clock Gating Technique for Power Optimization in SRAM and Sequential Circuit

Kumar¹,

Madhavi²,

Kishore³

2022

JAMRIS

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Low power VLSI designs are having wide variety of application usage in real-time. VLSI circuits are analyzed with various power reduction strategies. Existing approaches are used the clock frequency control, switching activity and scaling factor for power reduction. The glitching problem and clock triggering issues are higher therefore; the proposed work utilized the improved circuit of clock gating technique. In this proposed work, the enhanced clock gating with D-latch model is constructed to obtain the less power consumption. The traditional clock gating technique is improved by adding clock triggering on LATCH circuit and adding buffer circuit between the source and load circuitry to reduce the clock switching issues like gitching and clocking activity. Here the SRAM and sequential counter circuits are designed to utilize the power reduction strategy for improving the performance. This is applicable for various applications in real world and utilizing the FPGA and DSP application specific circuits. Experimental results are analyzed to obtain the power reduction result of SRAM and sequential circuit. Area, power, and delay are obtained the better results as compared with the previous work. Overall, design is performed using Xilinx 14.2 ISE suit.

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“…Many methodology, architecture and ideas has been proposed by researchers architecture level to device level but there is always a tradeoff between delay, area and power. So, according to the need of product or design the designer has to choose the appropriate technique [1][2][3][4]. Complementary metal oxide semiconductor (CMOS) has been used mostly for the VLSI designs.…”

Section: Introductionmentioning

confidence: 99%

Implementation and Modeling of Low Power Sleepy Stack Sram

Kakkar¹

2022

joas

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For the future technologies in which the devices and circuits are integrating more, low power consuming devices are needed. Mostly the reduction of power dissipation work is concentrated on switching and leakage current. However, sub threshold current is also a big factor which leads to power consumption especially for memories. In this paper, leakage power of SRAM memory cell is reduced by power gated sleepy stack structure which leads to lesser power dissipation. The power dissipation is reduced to 226 µW with proposed technique compared with power dissipation of conventional 6T SRAM cell which had 740 µW. With lesser power dissipation the circuit can have more battery backup and lesser heat emission

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Power optimization for VLSI circuits and systems

Cited by 11 publications

References 23 publications

Power Optimization Techniques for High Speed Processor Core in Sub 14nm Technology Node

Power Optimization Techniques for High Speed Processor Core in Sub 14nm Technology Node

Enhanced Clock Gating Technique for Power Optimization in SRAM and Sequential Circuit

Implementation and Modeling of Low Power Sleepy Stack Sram

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