Power optimization of LUT based FPGA circuits

Mashayekhi, Morteza; Jeddi, Zahra; Amini, Esmail

doi:10.1109/optim.2008.4602495

Cited by 1 publication

(1 citation statement)

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“…Mashayekhi, Jeddi and Amini [19] introduced methods which reduce switching within each LUT block by inserting fake registers and then using a re-timing method; the authors implemented their methods for two of ISCAS89 benchmark circuits and achieved a 25% power reduction over using similar re-timing methods without power reduction considerations.…”

Section: Dynamic Routing Power Reductionmentioning

confidence: 99%

Sa based power efficient FPGA LUT mapping

Dobson

Steinhöfel

2013

Proceedings of the 15th Annual Conference Companion on Genetic and Evolutionary Computation

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Look up Table (LUT) based Field Programmable Gate Arrays (FPGAs) are commonly used in mobile devices due to their efficient signal processing capabilities and flexibility to be reprogrammed in situ. However the mechanisms which enable a FPGA to be re-programmable make it require more power than an Application Specific Integrated Circuit. In this paper we consider the power reduction of a FPGA by optimising the mapping the underlying boolean circuit onto the LUT based FPGA with respect to cumulative switching. We formulate the power minimisation problem as a combinatorial optimisation problem. To tackle this NP hard problem we propose the application of a local search method. Here we introduce a complete a neighborhood function and apply heuristic simulated annealing in conjunction with the objective function from [20] 'cumulative switching'. Our experimental results show a 42.96% average reduction in power consumption compared to SIS based mapping and 27.44% average reduction in power consumption compared to a genetic algorithm.

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Section: Dynamic Routing Power Reductionmentioning

confidence: 99%