Power optimization of variable voltage core-based systems

Abstract

Abstract-The growing class of portable systems, such as personal computing and communication devices, has resulted in a new set of system design requirements, mainly characterized by dominant importance of power minimization and design reuse. The energy efficiency of systems-on-a-chip (SOC) could be much improved if one were to vary the supply voltage dynamically at run time. We develop the design methodology for the lowpower core-based real-time SOC based on dynamically variable voltage hardware. The key challenge is to develop effective scheduling techniques that treat voltage as a variable to be determined, in addition to the conventional task scheduling and allocation. Our synthesis technique also addresses the selection of the processor core and the determination of the instruction and data cache size and configuration so as to fully exploit dynamically variable voltage hardware, which results in significantly lower power consumption for a set of target applications than existing techniques. The highlight of the proposed approach is the nonpreemptive scheduling heuristic, which results in solutions very close to optimal ones for many test cases. The effectiveness of the approach is demonstrated on a variety of modern industrialstrength multimedia and communication applications. Index Terms-High-level synthesis, scheduling, synthesis for low power, system-on-a-chip (SOC).

Power Aware Scheduling of Bag-of-Tasks Applications with Deadline Constraints on DVS-enabled Clusters

“…Dynamic Voltage Scaling (DVS) is an efficient way to manage dynamic dissipation during computation [5,6]. The dynamic power consumption can be reduced by lowering the supply voltage of systems.…”

Mapping subtasks with multiple versions on an ad hoc grid

“…A significant amount of research has been performed in the areas of power constrained resource management in uniprocessors [12,25] and also in heterogeneous multiprocessors [20,26]. In all of these studies, power management is achieved through voltage scaling, which allows the reduction of the power usage by a CPU (which requires a reduction in clock frequency) at the expense of increasing the execution time of a task.…”

Power minimization in QoS sensitive systems

“…A number of researchers proposed the use of multiple voltages in order to reduce power consumption [6], [11], [15], [18]. Furthermore, several variable voltage techniques have been reported [8], [20]. Numerous algorithms for dynamic priority real-time systems have been proposed including [10], [19].…”