Power Optimized ADC-Based Serial Link Receiver

Chen, E-Hung; Yousry, Ramy; Yang, Chih-Kong Ken

doi:10.1109/jssc.2012.2185356

Cited by 47 publications

(10 citation statements)

References 13 publications

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“…We propose a different metric (more sensitive to the uncoded BER) and an iterative algorithm for optimizing our space-time slicer, choosing both sampling times and amplitude thresholds. The advantage of non-uniform thresholds for equalization has been reported in [8] [9]. We arrive at similar conclusions, as discussed in Section IV of the paper, but our results are more general with designs involving non-uniform thresholds spread across time.…”

Section: Summary Of Resultssupporting

confidence: 88%

“…We arrive at similar conclusions, as discussed in Section IV of the paper, but our results are more general with designs involving non-uniform thresholds spread across time. The DSP algorithms used in these references are simple DFE equalizers: 5 feedback taps and a single feedforward tap in [8], which is only applicable to channels with limited precursor intersymbol interference (ISI), and 2-3 feedforward taps with 2 feedback taps in [9]. Further, the numerical evaluations in [8][9] focus on a high SNR regime with very low BERs (∼ 10 −12 ).…”

Section: Summary Of Resultsmentioning

confidence: 99%

“…The DSP algorithms used in these references are simple DFE equalizers: 5 feedback taps and a single feedforward tap in [8], which is only applicable to channels with limited precursor intersymbol interference (ISI), and 2-3 feedforward taps with 2 feedback taps in [9]. Further, the numerical evaluations in [8][9] focus on a high SNR regime with very low BERs (∼ 10 −12 ). Since we are interested in understanding how far we can push simplification of the analog front end, we consider lower SNR regimes with uncoded BER of the order of 10 −3 − 10 −4 (which can be still be cleaned up easily with a lightweight channel code), and use optimal BCJR decoding based on the outputs from our space-time slicers.…”

Section: Summary Of Resultsmentioning

confidence: 99%

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Space-time slicer architectures for analog-to-information conversion in channel equalizers

Wadhwa

Madhow

Shanbhag

2014

2014 IEEE International Conference on Communications (ICC)

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Abstract-As modern communication transceivers scale to multi-Gbps speeds, the power consumption and cost of highresolution, high-speed analog-to-digital converters (ADCs) become a crucial bottleneck in realizing "mostly digital" receiver architectures that leverage Moore's law. This bottleneck could potentially be alleviated by designing analog front ends for the more specific goal of analog-to-information conversion (i.e., preserving the digital information residing in the received signal). As one possible approach towards this goal, we consider a generalization of the standard flash ADC: instead of implementing n bit quantization of a sample by passing it through 2 n − 1 slicers as in a standard ADC, the slicers are dispersed in time as well as space (i.e., amplitude). Considering BPSK over a dispersive channel, we first show, using ideas similar to those underlying compressive sensing, that randomly dispersing enough one-bit slicers over space and time does provide information sufficient for reliable demodulation over a dispersive channel. We then propose an iterative algorithm for optimizing the design of the sampling times and amplitude thresholds, and provide numerical results showing that the number of slicers can be significantly reduced relative to a conventional flash ADC with comparable bit error rate (BER). These system-level results motivate further investigation, in terms of both circuit and system design, into looking beyond conventional ADC architectures when designing analog front-ends for high-speed communication.

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Section: Summary Of Resultssupporting

confidence: 88%

Section: Summary Of Resultsmentioning

confidence: 99%

Section: Summary Of Resultsmentioning

confidence: 99%

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Space-time slicer architectures for analog-to-information conversion in channel equalizers

Wadhwa

Madhow

Shanbhag

2014

2014 IEEE International Conference on Communications (ICC)

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“…When loop unrolling is employed, the magnitude comparator and slicer can be merged with the front-end ADC by replacing the ADC reference levels with the precalculated equalizer slicing levels [4,5,8,26]. Fig.…”

Section: Digital Equalizermentioning

confidence: 99%

“…As the ever-growing demands for higher data rate call for more sophisticated equalization schemes and the advances in fabrication technology favor digital circuit implementation, backplane receivers that rely on a frontend analog-to-digital converter (ADC) and a digital equalizer are gaining more popularity in these years [1][2][3][4][5][6][7][8]. Such ADC-based receivers not only provide opportunity to utilize advanced digital signal processing (DSP) techniques to perform higher-level of equalization, but also enable more robust circuit implementation against process variation, leakage, and noise.…”

Section: Introductionmentioning

confidence: 99%

ADC-Based Backplane Receivers: Motivations, Issues and Future

Chung¹

2016

JSTS:Journal of Semiconductor Technology and Science

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Abstract-The analog-to-digital-converter-based (ADCbased) backplane receivers that consist of a front-end ADC followed by a digital equalizer are gaining more popularity in recent years, as they support more sophisticated equalization required for high data rates, scale better with fabrication technology, and are more immune to PVT variations. Unfortunately, designing an ADC-based receiver that meets tight power and performance budgets of high-speed backplane link systems is non-trivial as both frontend ADC and digital equalizer can be power consuming and complex when running at high speed. This paper reviews the state of art designs for the front-end ADC and digital equalizers to suggest implementation choices that can achieve high speed while maintaining low power consumption and complexity. Design-space exploration using systemlevel models of the ADC-based receiver allows through analysis on the impact of design parameters, providing useful information in optimizing the power and performance of the receiver at the early stage of design. The system-level simulation results with newer device parameters reveal that, although the power consumption of the ADC-based receiver may not comparable to the receivers with analog equalizers yet, they will become more attractive as the fabrication technology continues to scale as power consumption of digital equalizer scales well with process.

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