Power Performance Analysis of Digital Standard Cells for 28 nm Bulk CMOS at Cryogenic Temperature Using BSIM Models

Saligram, Rakshith; Chakraborty, Wriddhi; Cao, Ningyuan; Cao, Yu; Datta, Suman; Raychowdhury, Arijit

doi:10.1109/jxcdc.2021.3131100

Cited by 9 publications

(4 citation statements)

References 28 publications

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“…Figure 3 shows the temperature dependence of fresh (prestressed) I D -V G and g m characteristics. As reported in the previous literatures, [27][28][29][30][31] it is confirmed that the electrical characteristics are improved with decreasing temperature. In particular, the threshold voltage (V th ) is increased, the subthreshold slope (SS) is improved, and the transconductance (g m ) is improved.…”

Section: Resultssupporting

confidence: 87%

Study on the relation between interface trap creation and MOSFET degradation under channel hot carrier stressing at cryogenic temperatures

Suzuki,

Miyaki,

Mitani

2024

Jpn. J. Appl. Phys.

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In general, the degradation mechanism of MOSFETs has been discussed relating hydrogen. For instance, the interface traps are created due to the Si-H bond breakage at the MOS interface by hot carriers under electrical stressing. In addition, it is also reported that hydrogen also relates to the bulk trap creation. However, these hydrogen-related degradation mechanisms have been discussed based on the results within conventional measurement temperature region. However, the degradation mechanisms at cryogenic temperature have yet to be fully clarified. In this paper, the degradations of MOSFETs under a channel hot carrier stressing in the temperature range of 77 K ~ 300 K are investigated. Especially, we focus on the degradation of MOSFETs due to the interface trap creation. As a result, the MOSFETs degrade more under cryogenic temperature comparing to that near at the room temperature. This result implies the existing the additional degradation mechanism at cryogenic temperature.

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Section: Resultssupporting

confidence: 87%

Study on the relation between interface trap creation and MOSFET degradation under channel hot carrier stressing at cryogenic temperatures

Suzuki,

Miyaki,

Mitani

2024

Jpn. J. Appl. Phys.

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“…However, when temperature falls below 220 K, temperature coefficients of KT1, UTE, and PRT are not a constant anymore but varies with temperature, resulting in large fitting errors for simulating characteristics of MOSFETs using the standard BSIM models at cryogenic temperatures. Therefore, the inclusion of the additional temperature-dependent functions for these coefficients is required in order to improve the fitting precision for MOSFETs operation from 77 K to 300 K. For modeling the performance of MOSFETs at cryogenic temperatures, one has to tune key parameters at each temperature point in order to account for the varying device characteristics across the wide temperature range of 77 K-300 K [17], [31].…”

Section: Modeling Resultsmentioning

confidence: 99%

Temperature-Dependent Narrow Width Effects of 28-nm CMOS Transistors for Cold Electronics

Tsai

Lin

2022

IEEE J. Electron Devices Soc.

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We reported temperature-dependent narrow width effects on electrical characteristics of 28-nm CMOS transistors measured at temperature of 77 K−300 K. At cryogenic temperatures, P-MOSFETs appear to have stronger temperature-induced threshold voltage (V th ) increase and subthreshold swing (SS) reduction than N-MOSFETs, whereas the improvement in drain-induced barrier lowering (DIBL) is more evident in N-MOSFETs. N-MOSFETs show typical reverse narrow effect (RNWEs) in terms of V th roll-off along with SS rise-up with narrowing channel-widths (W G ). In contrast, P-MOSFETs exhibit anomalous RNWE, that is, V th (SS) decreases (increases) with decreasing W G from 3 µm to 0.6 µm and reversely increases (decreases) with further narrowing to 0.3 µm. RNWEs on N-MOSFETs are clearly suppressed at cryogenic temperatures, whereas P-MOSFETs appear to have enhanced anomalous RNWEs in terms of V th and DIBL variations at 77 K.INDEX TERMS Cryogenic CMOS, reverse narrow width effect.

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“…Figure 6. The device output characteristics for iso-overdrive voltage [10] The device transfer characteristics are shown for the linear region is shown in figure 7.…”

Section: The Characteristics Of Cmos Powermentioning

confidence: 99%

Analysing CMOS performance: A comprehensive study of operational characteristics in low-temperature environments

Cui

2024

J. Phys.: Conf. Ser.

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This article aims to methodically analyse and consolidate the experimental findings from previous research on the operational behaviour of Complementary Metal-Oxide-Semiconductor (CMOS) technology in low-temperature conditions. Recognizing the extensive array of empirical data available, the focus is on delineating and systematizing the functional attributes of CMOS devices when subjected to such environmental parameters. The study involves a comparative review of diverse scholarly sources, identifying and categorizing the operational features of CMOS in low-temperature scenarios. This endeavour seeks to distil these findings into clear, initial conclusions, drawing upon a comprehensive examination of relevant literature and database compilations. Structurally, the paper commences with an introductory exposition on CMOS, followed by a detailed literature review cantered on its performance in low-temperature contexts, leading to the analysis of collected data and ensuing discussions. The synthesis of these insights aims to enhance the understanding and generalization of CMOS operational dynamics in low-temperature environments, contributing to a cohesive body of knowledge in this specialized field.

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Power Performance Analysis of Digital Standard Cells for 28 nm Bulk CMOS at Cryogenic Temperature Using BSIM Models

Cited by 9 publications

References 28 publications

Study on the relation between interface trap creation and MOSFET degradation under channel hot carrier stressing at cryogenic temperatures

Study on the relation between interface trap creation and MOSFET degradation under channel hot carrier stressing at cryogenic temperatures

Temperature-Dependent Narrow Width Effects of 28-nm CMOS Transistors for Cold Electronics

Analysing CMOS performance: A comprehensive study of operational characteristics in low-temperature environments

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