Power, performance, and cost comparisons of monolithic 3D ICs and TSV-based 3D ICs

Nayak, Deepak Kumar; Banna, Srinivasa; Samal, Sandeep Kumar; Lim, Sung Kyu

doi:10.1109/s3s.2015.7333538

Cited by 29 publications

(11 citation statements)

References 4 publications

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“…Delay and power are obtained through post-P&R SPICE simulations to consider the interconnect parasitics for both 2D and 3D cases. For the 3D vias, we realistically estimate the resistance and capacitance to be 200mΩ and 0.1f F , respectively, based on similar monolithic 3D measurements on a FDSOI 28nm node [21].…”

Section: A Experimental Methodologymentioning

confidence: 99%

Area-Efficient Multiplier Designs Using a 3D Nanofabric Process Flow

Giacomin

Catthoor

Gaillardon

2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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In the past few years, the demand for computationally intensive applications, such as digital signal processing or convolutional neural networks, has grown exponentially. As they often rely on a significant number of multiply-and-accumulate cells, it is crucial to optimize their area and cost. Recently, a 3D Nanofabric flow has been proposed, where logic circuits are designed by stacking N identical vertical tiers on top of each other. Exploiting identical layers allows a fabrication process similar to the Vertical-NAND flash, where all the layers can be patterned at once. While the 3D Nanofabric flow presents several layout constraints (single metal routing and identical vertical layers), it can decrease the area by around one order of magnitude, leading to area-efficient and cost-effective circuits. In this paper, we propose to use the 3D Nanofabric process flow to design low-area multipliers. As multipliers can be designed using a regular array organization, we show how they can be spread across multiple vertical layers using the 3D Nanofabric flow, while respecting the different layout constraints. We then provide thorough circuit-level evaluations, including parasitics, to showcase the benefits of our proposed 3D multipliers at the circuit-level. We show that by stacking up to 64 layers to build a 64-input bit multiplier, the area and area-delayproduct can be decreased by 28.6× and 25.5×, respectively, compared to a traditional 2D implementation using a 28nm FDSOI technology, with only a 10% and 35% delay and power consumption overheads, respectively.

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Section: A Experimental Methodologymentioning

confidence: 99%

Area-Efficient Multiplier Designs Using a 3D Nanofabric Process Flow

Giacomin

Catthoor

Gaillardon

2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…Monolithic 3D ICs consist of multiple device layers fabricated sequentially on the same die and connecting using Monolithic Inter-tier Vias (MIVs) which are essentially the same size as intra-tier vias [27]. MIVs offer better parasitics and a higher integration density compared to TSVs due to their smaller size [28]. Since monolithic 3D enables the finest pitch of 3D connection, it holds the most promise.…”

Section: A Overview Of 3d Integration Technologiesmentioning

confidence: 99%

Thermal-Aware Design Space Exploration of 3-D Systolic ML Accelerators

Mathur

Kumar

John

et al. 2021

IEEE J. Explor. Solid-State Comput. Devices Circuits

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ML accelerators have a broad spectrum of usecases that pose different requirements on accelerator design for latency, energy, and area. In the case of systolic array-based ML accelerators, this puts different constraints on Processing Element (PE) array dimensions and SRAM buffer sizes. 3D integration packs more compute or memory in the same 2D footprint, which can be utilized to build more powerful or energyefficient accelerators. However, 3D also expands the design space of ML accelerators by additionally including different possible ways of partitioning the PE array and SRAM buffers among the vertical tiers. Moreover, the partitioning approach may also have different thermal implications. This work provides a systematic framework for performing system-level design space exploration of 3D systolic accelerators. Using this framework, different 3D-partitioned accelerator configurations are proposed and evaluated. The 3D-stacked accelerator designs are modeled using hybrid wafer bonding technique with a 1.44 µm pitch of 3D connection. Results show that different partitioning of the systolic array and SRAM buffers in a 4-tier 3D configuration can lead to either 1.1-3.9X latency reduction or 1-3X energy reduction compared to the baseline design of the same 2D area footprint. It is also shown that by carefully organizing the systolic array and SRAM tiers using logic over memory, the temperature rise with 3D across benchmarks can be limited to 6°C.

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“…Significant work has been done on the monolithic 3D IC design in recent times, most of which contributed to developing various design concepts of 3D ICs. The studies in this field include developing a face-to-face stacked heterogeneous 3D IC structure [13], exploring various microfluidic cooling mechanisms for 3D ICs [14], studying recent developments in monolithic 3D ICs and the high density and performance benefits [15], designing a logic-on-memory processor using monolithic 3D (M3D) IC techniques [16], developing a design and testing system for M3D ICs [17], comparing the TSV-based 3D structure with M3Ds [18,19], studying the effect of process variation on the performance of M3D ICs [20,21], and developing effective gate-sizing methods to boost circuit speed while considering intra-die process variation [22]. Other related studies include repurposing various components of commercial 2D P&R tools to implement 3D ICs [23][24][25][26].…”

Section: Introductionmentioning

confidence: 99%

Multi-Tier 3D IC Physical Design with Analytical Quadratic Partitioning Algorithm Using 2D P&R Tool

et al. 2021

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In this study, we developed a complete flow for the design of monolithic 3D ICs. We have taken the register-transfer level netlist of a circuit as the input and synthesized it to construct the gate-level netlist. Next, we partitioned the circuit using custom-made partitioning algorithms and implemented the place and route flow of the entire 3D IC by repurposing 2D electronic design automation tools. We implemented two different partitioning algorithms, namely the min-cut and the analytical quadratic (AQ) algorithms, to assign the cells in different tiers. We applied our flow on three different benchmark circuits and compared the total power dissipation of the 3D designs with their 2D counterparts. We also compared our results with that of similar works and obtained significantly better performance. Our two-tier 3D flow with AQ partitioner obtained 37.69%, 35.06%, and 12.15% power reduction compared to its 2D counterparts on the advanced encryption standard, floating-point unit, and fast Fourier transform benchmark circuits, respectively. Finally, we analyzed the type of circuits that are more applicable for a 3D layout and the impact of increasing the number of tiers of the 3D design on total power dissipation.

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Power, performance, and cost comparisons of monolithic 3D ICs and TSV-based 3D ICs

Cited by 29 publications

References 4 publications

Area-Efficient Multiplier Designs Using a 3D Nanofabric Process Flow

Area-Efficient Multiplier Designs Using a 3D Nanofabric Process Flow

Thermal-Aware Design Space Exploration of 3-D Systolic ML Accelerators

Multi-Tier 3D IC Physical Design with Analytical Quadratic Partitioning Algorithm Using 2D P&R Tool

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