Power-performance trade-offs for reconfigurable computing

Noguera, Juanjo; Badía, Rosa M.

doi:10.1145/1016720.1016751

Cited by 16 publications

(11 citation statements)

References 9 publications

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“…Thus, the PowerPC consumes 259.5 mW and 441 mW of power when clocked at 100 MHz and 300 MHz respectively. These numbers are in close agreement with [15], which also estimates the idle power of the PowerPC to be 50 mW. We obtain all power estimations at an ambient temperature of 25 o C. The highest measured power consumption of our hardware packet classifier is 180 mW when it processes a TCP packet with 100 rules.…”

Section: Power Consumptionsupporting

confidence: 82%

Smart-NICs: Power Proxying for Reduced Power Consumption in Network Edge Devices

Sabhanatarajan

Gordon‐Ross

Oden

et al. 2008

2008 IEEE Computer Society Annual Symposium on VLSI

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IntroductionWith the rapid increase in the number of edge devices connected to the Internet, the aggregate power consumption of these devices will become a major concern in the near future [2]. The most prevalent of these edge devices are consumer desktop computer systems, consuming on average 60 -95 watts of power and up to 195 watts in high-end systems [22].Research estimates that these systems are on average left idle for 75% of the time when powered on [18]. During these idle periods, systems could be powered down to a standby mode to reduce power consumption by 80% [2]. However, standby mode currently disrupts the system's network connectivity. Popular Internet applications such as peer to peer (P2P) clients and instant messengers demand continuous network connectivity in order to respond to incoming file queries and to announce a user's presence. In order to ensure this connectivity, users typically disable the power management features, inhibiting the transition to standby mode, and thereby increasing the energy consumption of otherwise idle systems. However, given existing system architectures, disabling standby mode is the only option to retain two-way network connectivity for user applications.A novel approach to address this problem is to augment the network interface card (NIC) to act as a proxy (or liaison) for the system during standby mode, and maintain network connectivity by handling a subset of certain application network protocol semantics [8][18]. This subset has the unique characteristic that responses do not require a complex decision process, thus the NIC can proxy automated responses, allowing the system to remain in standby mode -a technique known as power proxying. Network protocols that are amenable to proxying are called proxiable protocols. Purushothamom et al. [18] demonstrated that the NIC can successfully proxy portions of P2P application protocol semantics, increasing the amount of time a system can be in standby mode by 85%. Similarly, several other applications such as instant messengers, initiating sessions of Internet telephony, and new mail notification of email clients are suitable for power proxying.For a NIC to provide the capability of power proxying, power proxying rules are required to enable the NIC to identify packets that may be appropriately responded to using proxiable protocols. The system provides these rules to the NIC immediately prior to entering standby mode. Such a 'smart'-NIC (SNIC) would, upon receiving a packet, identify the packet and either respond appropriately or wake up the system.To provide this functionality, the SNIC must have a packet classifier, a method of examining incoming packets to determine the appropriate action. Thus, packet classification is the process of determining which rule an inbound packet satisfies. This packet classification methodology is similar to that performed in traditional routers. However, router techniques for packet classification are not directly applicable to a desktop NIC due to high resource requiremen...

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Section: Power Consumptionsupporting

confidence: 82%

Smart-NICs: Power Proxying for Reduced Power Consumption in Network Edge Devices

Sabhanatarajan

Gordon‐Ross

Oden

et al. 2008

2008 IEEE Computer Society Annual Symposium on VLSI

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“…Numerical data on the significant reconfiguration time for a CLB column confirms observations from previous researchers [4] that execution time for a task operating on a 8 8 block of 8-bit data is orders of magnitude lower than the reconfiguration overhead of such tasks. So, all our schedule length data is for processing a larger block corresponding to a 256 256 color image.…”

Section: Case Study Of Jpeg Encodersupporting

confidence: 79%

“…b) Resource constraints on FPGA: total number of columns being used for task executions and number of columns being reconfigured is limited by the total number of FPGA columns (4) Note that in this constraint we do not explicitly consider the effect of configuration prefetch, where there are columns that have been reconfigured, but not yet executed. Subsequent constraints e) and f) ensure correctness for columns used in configuration prefetch.…”

Section: ) Ilp Variablesmentioning

confidence: 99%

“…4 Note that in this equation and (3), we do not include the reconfiguration time for the initial set of tasks placed on the device. This enables us to accurately compare results with a traditional HW-SW partitioning formulation where execution time does not include system setup time of reconfiguration for the set of tasks placed on the device.…”

Section: ) Ilp Variablesmentioning

confidence: 99%

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Integrating Physical Constraints in HW-SW Partitioning for Architectures With Partial Dynamic Reconfiguration

Banerjee

Bozorgzadeh

Dutt

2006

IEEE Trans. VLSI Syst.

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Abstract-Partial dynamic reconfiguration is a key feature of modern reconfigurable architectures such as the Xilinx Virtex series of devices. However, this capability imposes strict placement constraints such that even exact system-level partitioning (and scheduling) formulations are not guaranteed to be physically realizable due to placement infeasibility. We first present an exact approach for hardware-software (HW-SW) partitioning that guarantees correctness of implementation by considering placement implications as an integral aspect of HW-SW partitioning. Our exact approach is based on integer linear programming (ILP) and considers key issues such as configuration prefetch for minimizing schedule length on the target single-context device. Next, we present a physically aware HW-SW partitioning heuristic that simultaneously partitions, schedules, and does linear placement of tasks on such devices. With the exact formulation, we confirm the necessity of physically-aware HW-SW partitioning for the target architecture. We demonstrate that our heuristic generates high-quality schedules by comparing the results with the exact formulation for small tests and with a popular, but placement-uanaware scheduling heuristic for a large set of over a hundred tests. Our final set of experiments is a case study of JPEG encoding-we demonstrate that our focus on physical considerations along with our consideration of multiple task implementation points enables our approach to be easily extended to handle heterogenous architectures (with specialized resources distributed between general purpose programmable logic columns). The execution time of our heuristic is very reasonable-task graphs with hundreds of nodes are processed (partitioned, scheduled, and placed) in a couple of minutes.Index Terms-Hardware-software (HW-SW) partitioning, linear placement, partial dynamic reconfiguration.

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“…4 At the transistor level, Padure et al, 5 have presented interesting results concerning the capacity of Threshold Logic Gate (TLG) circuits to be reconfigured at run time. Past research [7][8][9][10][11] in TLG has shown a significant reduction in the number of transistors required to implement combinatorial and sequential logic.…”

Section: Introductionmentioning

confidence: 99%

On-the-fly reconfigurable logic

Rajagopalan

Phillips

Abbott

2005

Smart Structures, Devices, and Systems II

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Reconfigurable Circuit (RC) platforms can be configured to implement complex combinatorial and sequential logic. In this paper we investigate various RC technologies and discuss possible methods to optimise their power, speed and area. To address the drawbacks of existing RC technologies we propose a generic architecture we call "OFRL" (On-the-Fly Reconfigurable Logic). Our objective is to provide a low power, high speed platform for reconfigurable circuit and dynamically reconfigurable logic applications that use fewer transistors than existing technologies.

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Power-performance trade-offs for reconfigurable computing

Cited by 16 publications

References 9 publications

Smart-NICs: Power Proxying for Reduced Power Consumption in Network Edge Devices

Smart-NICs: Power Proxying for Reduced Power Consumption in Network Edge Devices

Integrating Physical Constraints in HW-SW Partitioning for Architectures With Partial Dynamic Reconfiguration

On-the-fly reconfigurable logic

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