Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 With EDA Technofair
DOI: 10.1109/aspdac.1995.486194
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Power reduction by gate sizing with path-oriented slack calculation

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Cited by 20 publications
(2 citation statements)
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“…The column ''Reduction'' represents the percentage of the power reduction from the minimum-sized circuits estimated by our glitch estimation method and Eq. (8). The column ''Time'' indicates CPU times for the optimization on a SUN Ultra2.…”
Section: Conventional Methodsmentioning
confidence: 99%
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“…The column ''Reduction'' represents the percentage of the power reduction from the minimum-sized circuits estimated by our glitch estimation method and Eq. (8). The column ''Time'' indicates CPU times for the optimization on a SUN Ultra2.…”
Section: Conventional Methodsmentioning
confidence: 99%
“…[4,5,6]. Gate sizing has been utilized not only for delay optimization but also for power optimization [7,8,9,10]. The main idea of previous approaches for power reduction is to optimize the amount of capacitive load [7,8] or the amount of capacitive load and short-circuit current [9,10] based on the transition activity information obtained beforehand.…”
Section: ½ áòøöó ù ø óòmentioning
confidence: 99%