Power reduction by gate sizing with path-oriented slack calculation

Lin, How-Rern; Hwang, TingTing

doi:10.1145/224818.224827

Cited by 18 publications

(14 citation statements)

References 7 publications

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“…Gate/wire sizing and power optimization-Under a given timing constraint, budget management can be applied to find a set of nodes/edges in the netlist graph such that their physical size or power dissipation can be reduced by mapping to smaller, or powerefficient cell instances with larger delays from a target library [3,13,21]. Exploiting slack in high-level synthesis-There are several related work in the area of high-level synthesis where timing slack of the nodes in the data flow graphs are considered for better optimization in area and power.…”

Section: Related Workmentioning

confidence: 99%

A Unified Theory of Timing Budget Management

Ghiasi¹,

Bozorgzadeh

Huang

et al. 2006

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Section: Related Workmentioning

confidence: 99%

A Unified Theory of Timing Budget Management

Ghiasi¹,

Bozorgzadeh

Huang

et al. 2006

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Alternatively, one may start with the fastest possible design and then size down the gates along the paths with positive slack (compared to the given delay constraint) so as to maximize the reduction in switched capacitance. Another technique presented in [82], starts with a circuit that satisfies the timing constraint and sizes down certain gates (which are not necessarily on the non-critical paths) to reduce the power dissipation. The shortcoming of these approaches is their greedy nature which leads to sizing one gate a time.…”

Section: Transistor and Gate Sizingmentioning

confidence: 99%

Power minimization in IC design

Pedram

1996

ACM Trans. Des. Autom. Electron. Syst.

396

135

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Low power has emerged as a principal theme in today's electronics industry. The need for low power has caused a major paradigm shift in which power dissipation is as important as performance and area. This article presents an in-depth survey of CAD methodologies and techniques for designing low power digital CMOS circuits and systems and describes the many issues facing design-ers at architectural, logic and physical levels of design abstraction. It reviews some of the techniques and tools that have been proposed to overcome these difficulties and outlines the future challenges that must be met to design low power, high performance systems.

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“…The optimization problem of budgeting on the edges in a graph is formulated as a piece-wise linear objective function and solved using a modified graph-based Simplex algorithm ( [1]). Gate/wire sizing and power optimization-Under timing constraint, gate sizing problem is to find a set of nodes/edges in the graph such that their physical size can be reduced by mapping to smaller cell instances with larger delays from a target library [17], [18]. In general, delay budgeting can be applied during library mapping stage.…”

Section: Introductionmentioning

confidence: 99%

Optimal Integer Delay-Budget Assignment on Directed Acyclic Graphs

Bozorgzadeh

Ghiasi

Takahashi

et al. 2004

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Excess delay that each component of a design can tolerate under a given timing constraint is referred to as delay budget. Delay budgeting has been widely exploited to improve the design quality in VLSI CAD flow. The objective of the delay budgeting problem investigated in this paper is to maximize the total delay budget assigned to each node in a directed acyclic graph under a given timing constraint. Due to discreteness of the timing of the components in the libraries during design optimization flow, discrete solution for delay budgeting is essential. We present an optimal integer delay budgeting algorithm. We prove that the problem can be solved optimally in polynomial time. In addition, we look at different extensions of the delay budgeting problem, such as maximization of weighted summation of delay budgets assigned to the nodes with constraints on lower bound and upper bound on the delay budget allocated to each node. We prove that for both aforementioned extensions, our algorithm can produce an optimal integer solution in polynomial time. Our algorithm is generic and can be applied in different design tasks at different levels of abstraction. We applied our proposed optimal delay budgeting algorithm in library mapping during datapath synthesis on an FPGA platform ,using pre-optimized cores of FPGA libraries. For each application, we go through synthesis and place and route stages in order to obtain accurate results. Our optimal algorithm outperforms ZSA algorithm [4] in terms of area by ½¼± on average for all applications. In some applications, optimal delay budgeting can speedup runtime of place and route up to ¾ times.Index Terms-delay budgeting, timing constraint, core-based design implementations,integer programming.

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Power reduction by gate sizing with path-oriented slack calculation

Cited by 18 publications

References 7 publications

A Unified Theory of Timing Budget Management

A Unified Theory of Timing Budget Management

Power minimization in IC design

Optimal Integer Delay-Budget Assignment on Directed Acyclic Graphs

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