Power Reduction in Punch-Through Current-Based Electro-Thermal Annealing in Gate-All-Around FETs

Abstract

Device guidelines for reducing power with punch-through current annealing in gate-all-around (GAA) FETs were investigated based on three-dimensional (3D) simulations. We studied and compared how different geometric dimensions and materials of GAA FETs impact heat management when down-scaling. In order to maximize power efficiency during electro-thermal annealing (ETA), applying gate module engineering was more suitable than engineering the isolation or source drain modules.

Vacuum Inner Spacer to Improve Annealing Effect during Electro-Thermal Annealing of Nanosheet FETs

“…In this study, 3D simulations of the NS FETs with a vacuum inner spacer were performed using COMSOL Multiphysics software. The reason for using COMSOL is because it is the most useful tool for analyzing heat during ETA in nanoscale devices [ 8 , 12 ]. Heat transfer in both the solids module and the electric currents module was used.…”

“…Several approaches have been proposed to improve the annealing effect and to minimize the power consumption by modifying the device structure or materials [ 11 , 12 ]. However, these previous methods are not fully compatible with state-of-the-art logic transistors such as nanosheet FETs (NS FETs), since the backbone of the NS FET is completely different compared to conventional FinFETs and GAA FETs.…”

Editorial for the Special Issue on Recent Advances in Thin Film Electronic Devices

“…In addition to TFTs, the gate-all-around field-effect transistors (GAA FETs) were also simulated to find the mechanisms about reducing power with punch-through current annealing [8]. To maximize power efficiency during electro-thermal annealing, the application of gate module engineering was confirmed to be more suitable than the isolation or source drain modules.…”