Power Supply- and Temperature-Aware I/O Buffer Model for Signal-Power Integrity Simulation

Abstract

This paper presents the development and evaluation of a large-signal equivalent circuit model that accounts for the power supply fluctuation and temperature variation of I/O buffers circuit designed based on the fully depleted silicon on insulator (FDSOI) 28 nm process for signal-power integrity (SPI) simulation. A solid electrical analysis based on the working mechanisms of the nominal I/O buffer information specification- (IBIS-) like model is presented to support the derivation of an accurate and computationally efficient behavioral model that captures the essential effects of the power supply bouncing under temperature variation. The formulation and extraction of the Lagrange interpolating polynomial are investigated to extend the nominal equivalent circuit model. The generated behavioral model is implemented using the Newton-Neville’s formula and validated in simultaneous switching output buffers (SSO) scenario under temperature variation. The numerical results show a good prediction accuracy of the time domain voltage and current waveforms as well as the eye diagram of the high-speed communication I/O link while speeding-up the transient simulation compared to the transistor level model.

Analysis of Pre-Driver and Last-Stage Power—Ground-Induced Jitter at Different PVT Corners

“…In fact, the standard multiport behavioral model structure that describes the electrical behaviors of the IO buffer circuit, while considering the PGSV variables [7][8][9], is: Since these supplies are not constant due to high-current switching through the predriver's PDN, therefore, the IBIS model fails to accurately predict the timing distortion originating from V DD , the voltage noise which affects the output eye jitter. Moreover, previous works presented an extended equivalent circuit behavioral model for SiPI simulation in the pre-driver and the driver's last stage [10][11][12]. Moreover, ground supply noise has not been considered [12].…”

“…Moreover, previous works presented an extended equivalent circuit behavioral model for SiPI simulation in the pre-driver and the driver's last stage [10][11][12]. Moreover, ground supply noise has not been considered [12]. For these reasons, this paper explores the study of the separate effect of the jitter distortion induced by both stages powered by distinct P/G supplies.…”

Neural-Network Based Modeling of I/O Buffer Predriver under Power/Ground Supply Voltage Variations

“…A behavioral model based on input-output buffer information specifications (IBIS) or other parametric and enhanced equivalent circuit approaches can be used in SPI simulation flow that balances the tradeoff between simulation time and computational resources with good accuracy [ 2 , 3 ]. Nevertheless, previous nonlinear behavioral modelling methodologies focus mainly on improving the modelling of the last-stage of the I/O buffer [ 4 , 5 , 6 , 7 ]. In fact, voltage-time (V-t) tables capturing the predriver’s I/O timing distortions are extracted under fixed predriver’s power and ground supply voltage (PGSV) DC voltage.…”