POWER2: architecture and performance

White, Steven

doi:10.1109/cmpcon.1994.282902

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Virtual Multiporting1

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Cited by 3 publications

(1 citation statement)

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“…The IBM Power2 [45] and the Alpha 21264 [26] are two examples of processors that implement virtual multiporting to provide dual-ported access to a single-ported cache. Virtual multiporting utilizes time-division multiplexing to perform multiple accesses to a single-ported cache in a single cycle.…”

Section: Virtual Multiportingmentioning

confidence: 99%

Processor Microarchitecture: An Implementation Perspective

González

Latorre

Magklis

2010

Synthesis Lectures on Computer Architecture

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Section: Virtual Multiportingmentioning

confidence: 99%

Processor Microarchitecture: An Implementation Perspective

González

Latorre

Magklis

2010

Synthesis Lectures on Computer Architecture

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A compiler framework for restructuring data declarations to enhance cache and TLB effectiveness

Bacon¹,

Chow²,

Ju³

et al. 2010

CASCON First Decade High Impact Papers on - CASCON '10

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Fast message assembly using compact address relations

Dinda

O’Hallaron

1996

SIGMETRICS Perform. Eval. Rev.

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Message assembly and disassembly represent a significant fraction of total communication time in many parallel systems. We introduce a run-time approach for fast message assembly and disassembly. The approach is based on generating addresses by decoding a precomputed and compactly stored address relation that describes the mapping of addresses on the source node to addresses on the destination node. The main result is that relations induced by redistributions of regular block-cyclic distributed arrays can be encoded in an extremely compact form that facilitates high throughput message assembly and disassembly. We measure the throughput of decoding-based message assembly and disassembly on several systems and find performance on par with copy throughput.

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POWER2: architecture and performance

Cited by 3 publications

References 2 publications

Processor Microarchitecture: An Implementation Perspective

Processor Microarchitecture: An Implementation Perspective

A compiler framework for restructuring data declarations to enhance cache and TLB effectiveness

Fast message assembly using compact address relations

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