POWER2: Next generation of the RISC System/6000 family

Abstract

Next generation of the RlSC System/6000 family by S. W. White S. Dhawan Since its announcement, the IBM RISC System/6000@ processor has characterized the aggressive instruction-level parallelism approach to achieving performance. Recent enhancements to the architecture and implementation provide greater superscalar capability. This paper describes the architectural extensions which improve storage reference bandwidth, allow hardware square-root computation, and speed floating-point-to-integer conversion. The implementation, which exploits these extensions and doubles the number of functional units, is also described. A comparison of performance results on a variety of industry standard benchmarks demonstrates that superscalar capabilities are an attractive alternative to aggressive clock rates.

The Future Fast Fourier Transform?

“…The machine was configured with so-called thin nodes with 128 Mbytes of main memory. Thin nodes have a 66.7 MHz POWER2 processor [16], 64 Kbytes 4-way set associative level-1 data-cache, no level-2 cache, and a 64-bit-wide main memory bus. They have smaller data paths between the cache and the floating-point units than all other POWER2-based SP2 nodes.…”

Cluster assignment for high-performance embedded VLIW processors

“…One such approach (see, e.g., White and Dhawan [1994] and Ebcioglu et al [1998]) is based on the fact that the number of outputs of a functional unit (typically 1) is smaller than the number of inputs (typically 2). The idea is to write each result to several register files which makes it possible to reduce the number of read ports in each RF as illustrated in Figure 2.…”

Impact on performance of fused multiply-add units in aggressive VLIW architectures

“…This operation has been implemented in the floating-point units of the IBM RS/6000 [7], IBM POWER2 [28], MIPS R8000 [6] and MIPS R10000 [30] microprocessors. In the MIPS R10000, the FMA operation has been implemented by chaining the multiplier FPU output with the adder FPU input requiring rounding and alignment between them.…”

“…Several current microprocessors implement this operation (like the IBM RS/6000 [7] and POWER2 [28], and the MIPS R8000 [6] and R10000 [30]). This paper studies the influence of fused multiply-add functional units (fusion technique) in future ILP aggressive architectures.…”