PowerPC 601 and Alpha 21064: a tale of two RISCs

Smith, James E.; Weiss, Shlomo

doi:10.1109/2.294853

Cited by 36 publications

(14 citation statements)

References 6 publications

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“…In this paper, we set out to investigate the performance differences of these 2 processors. Other interesting processor studies in the past include a comparison of the PowerPC601 and Alpha 21064 [12], a detailed study of the Pentium Pro processor [5], a comparison of the SPARC and MIPS [7], etc.…”

Section: Introductionmentioning

confidence: 99%

A Tale of Two Processors: Revisiting the RISC-CISC Debate

Isen

John

2009

Computer Performance Evaluation and Benchmarking

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Abstract. The contentious debates between RISC and CISC have died down, and a CISC ISA, the x86 continues to be popular. Nowadays, processors with CISC-ISAs translate the CISC instructions into RISC style micro-operations (eg: uops of Intel and ROPS of AMD). The use of the uops (or ROPS) allows the use of RISC-style execution cores, and use of various micro-architectural techniques that can be easily implemented in RISC cores. This can easily allow CISC processors to approach RISC performance. However, CISC ISAs do have the additional burden of translating instructions to micro-operations. In a 1991 study between VAX and MIPS, Bhandarkar and Clark showed that after canceling out the code size advantage of CISC and the CPI advantage of RISC, the MIPS processor had an average 2.7x advantage over the studied CISC processor (VAX). A 1997 study on Alpha 21064 and the Intel Pentium Pro still showed 5% to 200% advantage for RISC for various SPEC CPU95 programs. A decade later and after introduction of interesting techniques such as fusion of micro-operations in the x86, we set off to compare a recent RISC and a recent CISC processor, the IBM POWER5+ and the Intel Woodcrest. We find that the SPEC CPU2006 programs are divided between those showing an advantage on POWER5+ or Woodcrest, narrowing down the 2.7x advantage to nearly 1.0. Our study points to the fact that if aggressive micro-architectural techniques for ILP and high performance can be carefully applied, a CISC ISA can be implemented to yield similar performance as RISC processors. Another interesting observation is that approximately 40% of all work done on the Woodcrest is wasteful execution in the mispredicted path.

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Section: Introductionmentioning

confidence: 99%

A Tale of Two Processors: Revisiting the RISC-CISC Debate

Isen

John

2009

Computer Performance Evaluation and Benchmarking

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“…Taking into consideration that DTSVLIW machines can be implemented with clock speed higher than equivalent Superscalar machines such as the PowerPC, it appears to be worth implementing DTSVLIW machines with current technology. Simple machines with fast clocks have proved to be more powerful than their more complex counterparts [32]. In addition, DTSVLIW machines using equivalent hardware can perform better than Superscalars [8,9].…”

Section: 14mentioning

confidence: 99%

Dynamically Scheduling VLIW Instructions

Souza

Rounce

2000

Journal of Parallel and Distributed Computing

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Very long instruction word (VLIW) machines potentially provide the most direct way to exploit instruction-level parallelism; however, they cannot be used to emulate current general-purpose instruction set architectures. In addition, programs scheduled for a particular implementation of a VLIW model cannot be guaranteed to be binary compatible with other implementations of the same machine model with a different number of functional units or functional units with different latencies. This paper describes an architecture, named dynamically trace scheduled VLIW (DTSVLIW), that can be used to implement machines that execute code of current RISC or CISC instruction set architectures in a VLIW fashion, with backward code compatibility. Preliminary measurements of the DTSVLIW performance, obtained with an execution-driven simulator running the SPECint95 benchmark suite, are also presented. Academic Press

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“…Taking in consideration that a DTSVLIW can be implemented with high-speed clock due to its VLIW-like simplicity, it appears to be worth a DTSVLIW implementation. Simple machines with fast clock have proved to be more powerful than their more complex counterparts [17]. Figure 9 shows a comparison between a DTSVLIW and a DIF machine.…”

Section: A Feasible Dtsvliw Implementationmentioning

confidence: 99%