PowerPlanningDL: Reliability-Aware Framework for On-Chip Power Grid Design using Deep Learning
Sukanta Dey,
Sukumar Nandi,
Gaurav Trivedi
Abstract:With the increase in the complexity of chip designs, VLSI physical design has become a time-consuming task, which is an iterative design process. Power planning is that part of the floorplanning in VLSI physical design where power grid networks are designed in order to provide adequate power to all the underlying functional blocks. Power planning also requires multiple iterative steps to create the power grid network while satisfying the allowed worst-case IR drop and Electromigration (EM) margin. For the firs… Show more
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