Practical Aspects of Quantization and Tamper-Sensitivity for Physically Obfuscated Keys

Immler, Vincent; Hennig, Maxim; Kürzinger, Ludwig; Sigl, Georg

doi:10.1145/2858930.2858933

Cited by 16 publications

(15 citation statements)

References 6 publications

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“…Based on the results of Section 8, we select ∆ M = 1 fF ≤ C c . Subsequent processing includes a quantization with bin size ∆ Q [IHKS16] as explained in Section 6.2. However, at this stage we are interested in the fundamental properties of the design only which is why we proceed with ∆ M instead.…”

Section: Stochastic Model Of a Sensor Nodementioning

confidence: 99%

“…The previously compensated and normalized data is now further processed by an equidistant quantization [IHKS16]. This is an error-reduction technique to mitigate the remaining circuit noise σ N that would otherwise cause frequent changes in the output data.…”

Section: Quantization and Error-correcting Code (Ecc)mentioning

confidence: 99%

“…Alternatives would have been, e.g., an equiprobable quantization as applied to the output of the Coating PUF [TSS + 06c] which is typically based on a Gray code, as illustrated in Figure 9b. However, the unequal width of equiprobable intervals causes helper data leakage in addition to an uneven tamper-sensitivity as explained in [IHKS16]. Other approaches to equiprobable quantization include [dGVL12, SAS17, BDHV07] using a partitioning scheme to avoid helper data leakage.…”

Section: Quantization and Error-correcting Code (Ecc)mentioning

confidence: 99%

“…To additionally reduce such errors, the offsets between each value X i and their corresponding interval center are stored as helper data W * . By following this approach, the probability of a quantization error can be significantly reduced, e.g., by choosing y = 3.29 the symbol error-rate is at 0.1% for each node [IHKS16]. During PUF reconstruction, this value is then mapped to the PUF response…”

Section: Quantization and Error-correcting Code (Ecc)mentioning

confidence: 99%

“…Its standard deviation σ is 2241 points which equals 29.58 fF. To compute the entropy, we apply an equidistant quantization [IHKS16]. Its bin size ∆ Q is chosen as multiples of the noise deviation σ N,Diff , thereby making the result more robust.…”

Section: Statistical Evaluation Of Differential Capacitance Measurementmentioning

confidence: 99%

See 4 more Smart Citations

Secure Physical Enclosures from Covers with Tamper-Resistance

Immler

Obermaier

et al. 2018

TCHES

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Ensuring physical security of multiple-chip embedded systems on a PCB is challenging, since the attacker can control the device in a hostile environment. To detect physical intruders as part of a layered approach to security, it is common to create a physical security boundary that is difficult to penetrate or remove, e.g., enclosures created from tamper-respondent envelopes or covers. Their physical integrity is usually checked by active sensing, i.e., a battery-backed circuit continuously monitors the enclosure. However, adoption is often hampered by the disadvantages of a battery and due to specialized equipment which is required to create the enclosure. In contrast, we present a batteryless tamper-resistant cover made from standard flexPCB technology, i.e., a commercially widespread, scalable, and proven technology. The cover comprises a fine mesh of electrodes and an evaluation unit underneath the cover checks their integrity by detecting short and open circuits. Additionally, it measures the capacitances between the electrodes of the mesh. Once its preliminary integrity is confirmed, a cryptographic key is derived from the capacitive measurements representing a PUF, to decrypt and authenticate sensitive data of the enclosed system. We demonstrate the feasibility of our concept, provide details on the layout, electrical properties of the cover, and explain the underlying security architecture. Practical results including statistics over a set of 115 flexPCB covers, physical attacks, and environmental testing support our design rationale. Hence, our work opens up a new direction of counteracting physical tampering without the need of batteries, while aiming at a physical security level comparable to FIPS 140-2 level 3.

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Section: Stochastic Model Of a Sensor Nodementioning

confidence: 99%

Section: Quantization and Error-correcting Code (Ecc)mentioning

confidence: 99%

Section: Quantization and Error-correcting Code (Ecc)mentioning

confidence: 99%

Section: Quantization and Error-correcting Code (Ecc)mentioning

confidence: 99%

Section: Statistical Evaluation Of Differential Capacitance Measurementmentioning

confidence: 99%

See 3 more Smart Citations

Secure Physical Enclosures from Covers with Tamper-Resistance

Immler

Obermaier

et al. 2018

TCHES

Self Cite

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show abstract

Variable-Length Bit Mapping and Error-Correcting Codes for Higher-Order Alphabet PUFs

Immler

Hiller

Liu

et al. 2017

Security, Privacy, and Applied Cryptography Engineering

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Review of error correction for PUFs and evaluation on state-of-the-art FPGAs

2020

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Efficient error correction and key derivation is a prerequisite to generate secure and reliable keys from PUFs. The most common methods can be divided into linear schemes and pointer-based schemes. This work compares the performance of several previous designs on an algorithmic level concerning the required number of PUF response bits, helper data bits, number of clock cycles, and FPGA slices for two scenarios. One targets the widely used key error probability of 10 −6 , while the other one requires a key error probability of 10 −9. In addition, we provide a wide span of new implementation results on state-of-the-art Xilinx FPGAs and set them in context to old synthesis results on legacy FPGAs.

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Practical Aspects of Quantization and Tamper-Sensitivity for Physically Obfuscated Keys

Cited by 16 publications

References 6 publications

Secure Physical Enclosures from Covers with Tamper-Resistance

Secure Physical Enclosures from Covers with Tamper-Resistance

Variable-Length Bit Mapping and Error-Correcting Codes for Higher-Order Alphabet PUFs

Review of error correction for PUFs and evaluation on state-of-the-art FPGAs

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