Practical LEEPL masks for sub-65-nm node

Yotsui, Kenta; Sumida, Tomoya; Negishi, Yoshiyuki; Yoshii, Takashi; Itoh, Kojiro; Tamura, Akira

doi:10.1117/12.570353

Cited by 1 publication

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“…For fabrication of single-membrane masks, we adopt a 'wafer-flow process, 9 in which stencil pattern is formed first, and the membrane is formed later. Figure 3 shows our wafer-flow process.…”

Section: Mask Fabrication Flow (Wafer-flow Process)mentioning

confidence: 99%

Experimental analysis of image placement accuracy of single-membrane masks for LEEPL

et al. 2005

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We have fabricated seven masks with different patterns on a 27 mm x 34 mm single-membrane for Low Energy Electron-beam Proximity Lithography (LEEPL) by the wafer-flow process. We have examined the membrane flatness and image placement (IP) accuracy, which are essential qualities to be assured. We summarize the results as follows: Masks with membranes of 13 MP and 20MPa stress satisfy the membrane flatness requirement of less than 2 µm while a mask with a 6 MPa membrane does not. Maps of the distortion induced by the wafer-flow process are obtained for the masks with 13 MPa and 20 MPa membranes and their performance is explained in terms of the contraction of the mask substrate. The out-of-plane distortion for a 3 mm x 3 mm block of dense hole patterns with an opening ratio, ranging from 10% to 40%, has been evaluated. The distortion induced by the block has been evaluated and the effect of the local magnification correction on the IP error is examined. Maps of the distortion induced by the wafer-flow process and 4 x 4 blocks of 10% and 20% opening are obtained for a mask with 13 MPa membrane and the distortion induced by the blocks is estimated in 3σ. The uncorrectable IP error for the mask with the blocks of 10% opening is estimated to be 10 nm (in 3σ), which satisfies the specification for LEEPL masks.

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Section: Mask Fabrication Flow (Wafer-flow Process)mentioning

confidence: 99%