2011
DOI: 10.1109/tasc.2011.2104930
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Practical Operation of Cryogen-Free Programmable Josephson Voltage Standards

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Cited by 13 publications
(4 citation statements)
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“…This feature of PJVS arrays has been exploited in this work by using some segments as power source and others as temperature sensor, using the procedure explained in Sec. III and previously adopted in [20] and [21].…”
Section: B Josephson Chipmentioning
confidence: 99%
“…This feature of PJVS arrays has been exploited in this work by using some segments as power source and others as temperature sensor, using the procedure explained in Sec. III and previously adopted in [20] and [21].…”
Section: B Josephson Chipmentioning
confidence: 99%
“…10 V PJVS devices are fabricated on a substrate of highpurity [15], 76.2 mm diameter silicon with 150 nm of thermal oxide. All lithography steps in this process are performed using an i-line wafer stepper with resolution of 0.4 μm.…”
Section: Fabrication Processmentioning
confidence: 99%
“…The residual thermal resistance is not low enough in the most demanding conditions and particular care is required in the design of a chip carrier to reduce thermal gradients, mainly at the interfaces between solid bodies. For JVSs working in the high-vacuum environment of a cryocooler, special cryopackages have been designed [6][7][8][9], exhibiting thermal resistances between chip and cold heat sink of few kelvin per watt. The case of JVS is particularly interesting and challenging: power levels of some tens of milliwatt are generally dissipated within a JVS, possibly causing its actual temperature to differ from that measured with the the sensor by hundreds of millikelvin.…”
Section: Introductionmentioning
confidence: 99%