Proceedings of the 4th ACM International Conference on Embedded Software 2004
DOI: 10.1145/1017753.1017767
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Practical PACE for embedded systems

Abstract: In current embedded systems, one of the major concerns is energy conservation. The dynamic voltage-scheduling (DVS) framework, which involves dynamically adjusting the voltage and frequency of the CPU, has become a well studied technique. It has been shown that if a task's computational requirement is only known probabilistically, there is no constant optimal speed for the task and the expected energy consumption is minimized by gradually increasing speed as thetaskprogresses [11].Itispossibletofindtheoptimal … Show more

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Cited by 75 publications
(76 citation statements)
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“…This assumption is validated extensively by both analytical models and measurement studies [14,23,36]. In practice, if a slower core consumes more power and thus energy than a fast one, it wont be built.…”
Section: Job Modelmentioning
confidence: 95%
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“…This assumption is validated extensively by both analytical models and measurement studies [14,23,36]. In practice, if a slower core consumes more power and thus energy than a fast one, it wont be built.…”
Section: Job Modelmentioning
confidence: 95%
“…Theorem 1 formalizes this property. While prior studies [23,27,36,39] show to use the "slow to fast" property under the maximum latency constraint in different contexts such as DVFS, in contrast, Theorem 1 is the first formal result that applies it to the more general case of any latency norm constraint and with multiple latency norm constraints. Theorem 1.…”
Section: An Optimal Schedule Migrates From Slow To Fast Coresmentioning
confidence: 97%
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