Practical repeater insertion for low power

Liu, Xun; Peng, Yuantao; Papaefthymiou, Marios C.

doi:10.1145/996566.996576

Cited by 14 publications

(3 citation statements)

References 33 publications

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“…Several circuit models have been proposed to compute the delay or power dissipation of repeaters such as the switch-level RC model [9], the generalized model considering slew rate [14], and the moment matching model [3]. Various design objectives are used such as delay minimization [4,12,19], power minimization [6,10,13,16,18], and cross-coupling noise reduction [1,7].…”

Section: Previous Researchmentioning

confidence: 99%

Freeze: engineering a fast repeater insertion solver for power minimization using the ellipsoid method

Peng¹,

Liu²

2005

Proceedings. 42nd Design Automation Conference, 2005.

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This paper presents a novel repeater insertion algorithm for the power minimization of realistic interconnect trees under given timing budgets. Our algorithm judiciously combines a local optimizer based on the dynamic programming technique and a global search engine using the ellipsoid method. As a result, our approach is capable of producing high-quality solutions at a very fast speed. Furthermore, our scheme is robust and does not need any manual tuning of the iteration-control parameters.We have developed a repeater insertion tool, called FREEZE, using the proposed algorithm and applied it to various interconnect trees with different timing targets. Experimental results demonstrate the high effectiveness of our approach. In comparison with the state-of-the-art low-power repeater insertion schemes, FREEZE requires 5.8 times fewer iterations on the average, achieving up to 27 times speedup with even better power savings. When compared with a dynamic programming based scheme, which guarantees the optimal solution, our tool delivers up to 50 times speedup with 0.9% power increase on the average.

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Section: Previous Researchmentioning

confidence: 99%

Freeze: engineering a fast repeater insertion solver for power minimization using the ellipsoid method

Peng¹,

Liu²

2005

Proceedings. 42nd Design Automation Conference, 2005.

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“…the insertion of sequential elements (or clocked buffers) to pipeline long wires in shorter segments whose delays meet T clk [3,6,14,15,21]. By providing one or more extra clock periods to traverse long distances, wire pipelining trade-offs latency for throughput.…”

Section: Introductionmentioning

confidence: 99%

Distributed flit-buffer flow control for networks-on-chip

Concer

Petracca

Carloni

2008

Proceedings of the 6th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis

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The combination of flit-buffer flow control methods and latency-insensitive protocols is an effective solution for networks-on-chip (NoC). Since they both rely on backpressure, the two techniques are easy to combine while offering complementary advantages: low complexity of router design and the ability to cope with long communication channels via automatic wire pipelining. We study various alternative implementations of this idea by considering the combination of three different types of flit-buffer flow control methods and two different classes of channel repeaters (based respectively on flip-flops and relay stations). We characterize the area and performance of the two most promising alternative implementations for NoCs by completing the RTL design and logic synthesis of the repeaters and routers for different channel parallelisms. Finally, we derive high-level abstractions of our circuit designs and we use them to perform system-level simulations under various scenarios for two distinct NoC topologies and various applications. Based on our comparative analysis and experimental results, we propose a NoC design approach that combines the reduction of the router queues to a minimum size with the distribution of flit buffering onto the channels. This approach provides precious flexibility during the physical design phase for many NoCs, particularly in those systems-on-chip that must be designed to meet a tight constraint on the target clock frequency.

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“…Various design objectives have been used, including delay minimization [3,13,19], power minimization [5,11,14,17,18], and cross-coupling noise reduction [1,6]. Repeater insertion algorithms can be classified as either analytical approaches [5,7,15] or DP-based approaches [12,16].…”

Section: Introductionmentioning

confidence: 99%

A sensitivity analysis of low-power repeater insertion

Peng

Liu

2005

Proceedings of the 15th ACM Great Lakes Symposium on VLSI

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In this paper, we perform the first quantitative study on the sensitivities of repeater power to available repeater width and candidate location, two key parameters of the dynamic programming (DP) based repeater insertion algorithms. Based on our analysis, we propose a simple yet effective scheme to select repeater widths and locations for DP-based algorithms, achieving an excellent tradeoff between the solution quality and runtime. Experimental results have shown that, when combined with our sensitivity-guided scheme, the DP algorithm can attain more than 6 times speedup with negligible power degradation.

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Practical repeater insertion for low power

Cited by 14 publications

References 33 publications

Freeze: engineering a fast repeater insertion solver for power minimization using the ellipsoid method

Freeze: engineering a fast repeater insertion solver for power minimization using the ellipsoid method

Distributed flit-buffer flow control for networks-on-chip

A sensitivity analysis of low-power repeater insertion

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