Practical Strategies for Power-Efficient Computing Technologies

Abstract

| After decades of continuous scaling, further advancement of silicon microelectronics across the entire spectrum of computing applications is today limited by power dissipation. While the trade-off between power and performance is well-recognized, most recent studies focus on the extreme ends of this balance. By concentrating instead on an intermediate range, an $ 8Â improvement in power efficiency can be attained without system performance loss in parallelizable applicationsVthose in which such efficiency is most critical. It is argued that power-efficient hardware is fundamentally limited by voltage scaling, which can be achieved only by blurring the boundaries between devices, circuits, and systems and cannot be realized by addressing any one area alone. By simultaneously considering all three perspectives, the major issues involved in improving power efficiency in light of performance and area constraints are identified. Solutions for the critical elements of a practical computing system are discussed, including the underlying logic device, associated cache memory, off-chip interconnect, and power delivery system. The IBM Blue Gene system is then presented as a case study to exemplify several proposed directions. Going forward, further power reduction may demand radical changes in device technologies and computer architecture; hence, a few such promising methods are briefly considered.

Extreme-scale computer architecture: Energy efficiency from the ground up

“…There is evidence that the most energy-efficient operating point corresponds to a V dd value somewhat higher than the threshold voltage (V th ) of the transistor [3]. This corresponds to a regime that has been called Near-Threshold Computing (NTC) [4], [5], [6]. Roughly speaking, for current technology, this corresponds to a V dd of about 500 mV rather than the conventional 1 V.…”

“…While there are several unclear aspects with NTC, it can potentially decrease the power consumption by more than 40 times [4], [5]. This is a substantial reduction, and implies that many more cores can now be placed on a given powerconstrained chip.…”

VARIUS-NTV: A microarchitectural model to capture the increased sensitivity of manycores to process variations at near-threshold voltages

“…This environment is called Near-Threshold Computing (NTC) [7], [13], [28] -as opposed to conventional Super-Threshold Computing (STC). V dd is a most powerful knob because it impacts both dynamic and static energy super-linearly.…”

“…V dd is a most powerful knob because it impacts both dynamic and static energy super-linearly. Current indications suggest that NTC can decrease the energy per operation by several times over STC [7], [13]. A drawback is that it imposes a frequency reduction, which may be tolerable through more parallelism in the application.…”

“…Near-Threshold Computing (NTC) Basics NTC refers to an environment where V dd is set to a value only slightly higher than the transistors' V th [7], [13], [28]. For current technologies, this roughly corresponds to V dd ≈500mV, while the V dd of conventional (or STC) environments is ≈1V.…”