Pre-clean Study for Both Damascene SiN and N-Blok to Resolve Queue-time-dependent Dielectric Barrier VBD Degradation

Abstract

Recently, it was found that for 65 nm logic device the VBD for SiN will decrease dramatically (from about 60 V to below 30-40 V if the queue is longer than eight hours) when the queue time after Cu CMP (prior to damascene SiN deposition) is longer than two hours. The problem happened most at SiN and BD I interface (Metal layer 5 with the same design rule of line spacing of Metal layer 2). Such a problem makes the BEOL production extremely difficult. To overcome this major challenge for SiN, we have analyzed the various kinds of potential root causes and showed that the change of Cu oxidation post Cu CMP is the real root cause. We have developed a series of new pre-clean recipes and tested most of them at customer site with customer's device wafers together with CVD division at the 300 mm fab of Applied Materials in USA. In this paper, we will discuss the potential mechanisms of time dependant VBD degradation and the practical solution to this problem.