Precise Cache Profiling for Studying Radiation Effects

Abstract

Increased access to space has led to an increase in the usage of commodity processors in radiation environments. These processors are vulnerable to transient faults such as single event upsets that may cause bit-flips in processor components. Caches in particular are vulnerable due to their relatively large area, yet are often omitted from fault injection testing because many processors do not provide direct access to cache contents and they are often not fully modeled by simulators. The performance benefits of caches make disabling them undesirable, and the presence of error correcting codes is insufficient to correct for increasingly common multiple bit upsets. This work explores building a program’s cache profile by collecting cache usage information at an instruction granularity via commonly available on-chip debugging interfaces. The profile provides a tighter bound than cache utilization for cache vulnerability estimates (50% for several benchmarks). This can be applied to reduce the number of fault injections required to characterize behavior by at least two-thirds for the benchmarks we examine. The profile enables future work in hardware fault injection for caches that avoids the biases of existing techniques.

Debugging Xilinx Zynq-7000 SoC Processor Caches during Linux System Execution under Proton Irradiation

“…The reason can be wrong addresses or wrong register values during execution. This matches with the findings in [3] where it was shown, that most crashes do not occur due to false cache data, but in large processing pipelines.…”

“…This is an error class directly concerned with the caches, as data can potentially be loaded from the RAM to the caches before its needed, for example large sequentially accessed datasets. This prefetch mechanism might be error prone under irradiation as it was also shown to cause crashes with an anomalous cache counter [3]. Technically, the prefetch function can also be disabled as a work-around.…”