Precise chip and package 3D capacitance simulations of realistic interconnects using a general purpose FEM-tool

Abstract

This paper describes on-and 08-chip 3 0 capacitance simulations utilizing the general purpose FEM system ANSYS-MulhphysicsN extended with an APDL macro f o r capacitance simulations. This facilitates the use of the advanced 3 0 capabilities of ANSYS"' to genemte, edir and visualize realistically shaped 3 0 structures.