Precision and error analysis of MATLAB applications during automated hardware synthesis for FPGAs

Abstract

We present a compiler that takes high level signal and image processing algorithms described in MATLAB and generates an optimized hardware for an FPGA with external memory. We propose a precision analysis algorithm to determine the minimum number of bits required by an integer variable and a combined precision and error analysis algorithm to infer the minimum number of bits required by a floating point variable. Our results show that on an average, our algorithms generate hardware requiring a factor of 5 less FPGA resources in terms of the Configurable Logic Blocks (CLBs) consumed as compared to the hardware generated without these optimizations. We show that our analysis results in the reduction in the size of lookup tables for functions like sin, cos, sqrt, exp etc. Our precision analysis also enables us to pack various array elements into a single memory location to reduce the number of external memory accesses. We show that such a technique improves the performance of the generated hardware by an average of 35%.

Wordlength optimization for linear digital signal processing

“…Some published approaches to the wordlength optimization problem use an analytic approach to scaling and/or error estimation [5], [7], [9], some use simulation [6], [8], and some use a hybrid of the two [10]. The advantage of analytic techniques is that they do not require representative simulation stimulus, and can be faster, however, they tend to be more pessimistic.…”

“…There is little analytical work on supporting dataflow graphs containing cycles, although in [9], finite loop bounds are supported. Some published approaches use worst-case instantaneous error as a measure of signal quality [5], [7], [8] whereas some use signal-to-noise ratio (SNR) [1], [6]. The proposals in this paper use fully analytic error models, use SNR as a quality metric, and can be applied to dataflow graphs containing cycles without the pessimism exhibited by other analytic work.…”

“…All signals in the model of [7] must have equal fractional precision; the authors propose an analytic worst-case error model in order to estimate the required number of fractional bits. Area reductions of 80% combined with speed increases of 20% are reported when compared to a uniform 32-bit representation.…”

“…The MATCH Project [7] also uses range propagation through dataflow graphs, except variables with a fractional component are allowed. All signals in the model of [7] must have equal fractional precision; the authors propose an analytic worst-case error model in order to estimate the required number of fractional bits.…”

“…There are, however, several published approaches to wordlength optimization. Those offering an area/signal quality tradeoff are of a heuristic nature [1], [5], [6] do not support different fractional precision for different internal variables [7], or assume that arithmetic error falls monotonically in each signal wordlength [6], [8]. In contrast, this paper proposes techniques which capture the full complexity of the error constraint surface, allow multiple fractional precisions, and provide the choice of a heuristic or an optimum solution (with respect to the area and error models).…”