Precision, Recall, and Sensitivity of Monitoring Partially Synchronous Distributed Systems

Yingchareonthawornchai, Sorrachai; Nguyen, D.; Valapil, Vidhya Tekken; Kulkarni, Sandeep S.; Demirbaş, Murat

doi:10.48550/arxiv.1607.03369

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“…Because of some synchronization, HVC timestamp size may be less than n while preserving properties of VC [23]. In partial synchrony, the trade-off in terms of precision and recall monitoring was discussed in [22]. Namely, Hybrid Logical Clocks (HLC) [14] have been used for efficient predicate detection when imperfect recall is acceptable [24].…”

Section: Related Workmentioning

confidence: 99%

Monitoring Partially Synchronous Distributed Systems Using SMT Solvers

Valapil

Yingchareonthawornchai

Kulkarni

et al. 2017

Runtime Verification

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In this paper, we discuss the feasibility of monitoring partially synchronous distributed systems to detect latent bugs, i.e., errors caused by concurrency and race conditions among concurrent processes. We present a monitoring framework where we model both system constraints and latent bugs as Satisfiability Modulo Theories (SMT) formulas, and we detect the presence of latent bugs using an SMT solver. We demonstrate the feasibility of our framework using both synthetic applications where latent bugs occur at any time with random probability and an application involving exclusive access to a shared resource with a subtle timing bug. We illustrate how the time required for verification is affected by parameters such as communication frequency, latency, and clock skew. Our results show that our framework can be used for real-life applications, and because our framework uses SMT solvers, the range of appropriate applications will increase as these solvers become more efficient over time.

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Section: Related Workmentioning

confidence: 99%