Preconditioned Conjugate Gradient Acceleration on FPGA-Based Platforms

Abstract

Reconfigurable computing can significantly improve the performance and energy efficiency of many applications. However, FPGA-based chips are evolving rapidly, increasing the difficulty of evaluating the impact of new capabilities such as HBM and high-speed links. In this paper, a real-world application was implemented on different FPGAs in order to better understand the new capabilities of modern FPGAs and how new FPGA technology improves performance and scalability. The aforementioned application was the preconditioned conjugate gradient (PCG) method that is utilized in underground analysis. The implementation was done on four different FPGAs, including an MPSoC, taking into account each platform’s characteristics. The results show that today’s FPGA-based chips offer eight times better performance on a memory-bound problem than 5-year-old FPGAs, as they incorporate HBM and can operate at higher clock frequencies.

Accelerating SpMV on FPGAs Through Block-Row Compress: A Task-Based Approach

“…However, unlike our design, even VSpMV architecture, as is, is not able to perform the generic form of SpMV (y = α•A×x+β •y) and does not fully exploit available HBM bandwidth. Other works have experimented with double-precision SpMV implementations on FPGAs with HBM [13], [14]. In both cases, however, their main goal is to evaluate different aspects of memory bandwidth management, not to improve SpMV arithmetic performance.…”