Predictability and Efficiency in Contemporary Hard RTOS for Multiprocessor Systems

Nogueira, Andre; Calha, Mario

doi:10.1109/rtcsa.2011.56

Cited by 3 publications

(1 citation statement)

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“…A cache is one of the essential hardware parts because it could improve system performance. The cache can reduce computation time but can also cause interference between tasks in multi-core architectures (e.g., cache miss because of shared cache cleaning for the private cache replacement of other cores) [6]. When a cache miss occurs, data is relocated from the main memory based on the memory hierarchy.…”

Section: Introductionmentioning

confidence: 99%

Software-Level Memory Regulation to Reduce Execution Time Variation on Multicore Real-Time Systems

2022

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Modern real-time embedded systems are equipped with multi-core processors to execute computationally intensive tasks. In multi-core architecture, last-level cache memory is shared by cores. The shared cache becomes a non-deterministic resource, which affects the independent execution of real-time tasks. We propose a solution to remedy a variation in execution time when interference happens in a shared cache. Current solutions have relied on memory scheduling approaches that avoid concurrent memory access to guarantee deterministic execution time. However, these methods required complex analysis to accurately estimate the worst-case execution time and to schedule tasks in an overly conservative manner. Unlike existing works, the proposed method prevents simultaneous memory access using the side effect of memory barriers rather than the complicated analysis. A memory barrier is inserted based on a simple code analysis that is performed in units of basic blocks using the LLVM compiler. The proposed method not only does not require the modification of the operating system or task execution flow but also relatively shows fast analysis time. Experimental results show that the proposed basic block-based memory barrier insertion method can reduce the variation in execution time by up to 80% when interference occurs.INDEX TERMS code analysis, embedded systems, multi-core architecture, real-time systems, shared cache interference

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Section: Introductionmentioning

confidence: 99%