Predictability of load/store instruction latencies

Abstract

I n this paper we present a model of coarse grain dataflow execution. We present one top down and two bottom up methods for generation of multithreaded code, and evaluate their effectiveness. The bottom up techniques start form a fine-grain dataflow graph and coalesce this into coarse-grain clusters. The top down technique generates clusters directly from the intermediate data dependence graph used for compiler opfimizations. We discuss the relevant phases in the compilation process. We compare the effectiveness of the strategies by measuring the total number of clusters executed, the total number of instructions executed, cluster size, and number of matches per cluster. It turns out that the top down method generates more efficient code, and larger clusters. However the number of matches per cluster is larger for the top down method, which could incur higher cluster synchronization costs.

Managing data caches using selective cache line replacement

“…A lower value proved too aggressive in removing load references from using the cache, and a higher value did not remove a sufficient number of load instructions to help performance. Furthermore, the 75% threshold also relates to the memory bandwidth requirements for a cache line replacement (32 bytes) and a 64-bit load reference (8 bytes), and is the same value settled on by [ASWR93]. Table 3 shows the change in cache hit rate and required memory bandwidth after the poorest performing instructions were marked C/NA.…”

“…[ASWR93] did not look at an extensive set of benchmark programs, we began by performing experiments similar to theirs in which we measured the miss rate associated with individual load and store instructions for a more extensive set of programs. Using the ATOM program trace facilities [SrEu94] and the SPEC92 suite of benchmarks, such statistics were relatively straight-forward to gather.…”

“…Thus, a cache lookup for an item is unaffected by whether it is marked C/NA or not ---only the allocation on a miss is affected. We looked at both static (similar to [ASWR93]) and dynamic approaches to identifying and marking these C/NA instructions.…”

Software prefetching for software pipelined loops

“…When software pipelining is applied in VLIW architectures, where instruction latencies and scheduling are fixed at compile-time, execution time can be highly degraded due to the stall time provoked by dependences with memory instructions. Even if a nonblocking cache is used, true dependences with previous memory operations at a near distance 1 can make the processor to stall afterwards. The choice of scheduling all loads using the cache-miss latency requires considerable ILP and increases register pressure( [1]).…”

“…Even if a nonblocking cache is used, true dependences with previous memory operations at a near distance 1 can make the processor to stall afterwards. The choice of scheduling all loads using the cache-miss latency requires considerable ILP and increases register pressure( [1]). …”