Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow

Abstract

This paper studies the prediction of interconnect delay in an industrial setting. Industrial circuits and two industrial FPGA architectures were used in the study. We show that there is a large amount of inherent randomness in a state-ofthe-art FPGA placement algorithm. Thus, it is impossible to predict interconnect delay with a high degree of accuracy. Futhermore, we show that a simple timing model can be used to predict some aspects of interconnect timing with just as much accuracy as predictions obtained by running the placement tool itself. Using this simple timing model in a two-phase timing driven physical synthesis flow can both improve quality of results and decrease runtime. Next, we present a metric for predicting the accuracy of our interconnect delay model and show how this metric can be used to reduce the runtime of a timing driven physical synthesis flow. Finally, we examine the benefits of using the simple timing model in a timing driven physical synthesis flow, and attempt to establish an upper bound on these possible gains, given the difficulty of interconnect delay prediction.

Analyzing and predicting the impact of CAD algorithm noise on FPGA speed performance and power

“…At the preplacement stage, work has been done to predict interconnect wirelength and delay [8,13]. The work by Manohararajah et al [8] proposed a simple timing model based on using a single delay value for each connection depending on its source and destination node type and port (e.g. logic, I/O, memory).…”

An Analytical Model Relating FPGA Architecture to Logic Density and Depth

“…Smith et al presents a model to estimate post-placement wirelength for both homogeneous and hetergenous FPGA architectures [18]. There has also been work providing early stage delay values for FPGAs by Manohararajah [19], which uses a lookup table with pre-recorded values of interconnect delays as a function of architecture parameters.…”

“…Measured results for d k are gathered by recording the maximum depth for the benchmark circuits after they are technology mapped using Flow-Map [21]. Analytical results are obtained by using the measured d 2 and Equation 19. The d 2 values are measured from the 2-input netlist of the benchmark circuits.…”

Estimating circuit delays in FPGAs after technology mapping

“…However, similar literature can be found: extensive research considered local wirelength estimations [5] and total wirelength estimations [4]. In [3] fast placement was used as an early timing feedback model for improved technology mapping.…”

“…Both depend on the wirelength behavior. Studies have been dedicated to the estimation of local [5] and global [4] wirelengths, but to our knowledge both performance estimations and identification of the critical zone are not present in literature. Therefore this paper, firstly, presents a comparison of three performance estimation techniques: logic depth, Monte Carlo simulation and fast placement (ordered from low to high accuracy and runtime).…”