Predicting the number of fatal soft errors in Los Alamos national laboratory's ASC Q supercomputer

Michalak, Sarah; Harris, K.W.; Hengartner, Nicolas W.; Takala, B.E.; Wender, S. A.

doi:10.1109/tdmr.2005.855685

Cited by 125 publications

(59 citation statements)

References 17 publications

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“…These soft errors do not cause permanent hardware damage, but may result in a complete system failure. For example, Sun Microsystems acknowledges that customers such as America Online, eBay and Los Alamos National Labs experienced system failures caused by transient faults [8].…”

Section: Introductionmentioning

confidence: 99%

DAFT: Decoupled Acyclic Fault Tolerance

Zhang

Lee

Johnson

et al. 2011

Int J Parallel Prog

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Higher transistor counts, lower voltage levels, and reduced noise margin increase the susceptibility of multicore processors to transient faults. Redundant hardware modules can detect such errors, but software transient fault detection techniques are more appealing for their low cost and flexibility. Recent software proposals double register pressure or memory usage, or are too slow in the absence of hardware extensions, preventing widespread acceptance. This paper presents DAFT, a fast, safe, and memory efficient transient fault detection framework for commodity multicore systems. DAFT replicates computation across multiple cores and schedules fault detection off the critical path. Where possible, values are speculated to be correct and only communicated to the redundant thread at essential program points. DAFT is implemented in the LLVM compiler framework and evaluated using SPEC CPU2000 and SPEC CPU2006 benchmarks on a commodity multicore system. Results demonstrate DAFT's high performance and broad fault coverage. Speculation allows DAFT to reduce the performance overhead of software redundant multithreading from an average of 200% to 38% with no degradation of fault coverage.

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Section: Introductionmentioning

confidence: 99%

DAFT: Decoupled Acyclic Fault Tolerance

Zhang

Lee

Johnson

et al. 2011

Int J Parallel Prog

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“…For example, the 100,000 node BlueGene/L scheme at Lawrence Livermore National Laboratory (LLNL) practices an L1 cache bit error every 8 hours [36] and a hard failure every 7-10 days. Exascale schemes are expected to fail every 3-26 minutes [37], [38].…”

Section: Related Workmentioning

confidence: 99%

IMCLA: Performance Evaluation of Integrated Multilevel Checkpointing Algorithms using Checkpointing Efficiency

Singh¹,

Chhabra²,

Singh³

2013

Int. J. Com. Dig. Sys.

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Main objective of this research work is to improve the checkpoint efficiency for integrated multilevel checkpointing algorithms (IMLCA) and prevent checkpointing from becoming the bottleneck of cloud data centers. In order to find an efficient checkpoint interval, checkpointing overheads has also considered in this paper. Traditional checkpointing methods stores persistently snapshots of the present job state and use them for resuming the execution at a later time. The attention of this research is strategies for deciding when and whether a checkpoint should be taken and evaluating them in regard to minimizing the induced monetary costs. By varying rerun time of checkpoints performance comparisons are which will be used to evaluate optimal checkpoint interval. The purposed fail-over strategy will work on application layer and provide highly availability for Platform as a Service (PaaS) feature of cloud computing.

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“…In 2005, Hewlett Packard stated that on a 2048-node supercomputer in Los Alamos National Laboratory, a higher-than-expected number of single-node failures were observed and the primary cause of these failures were transient faults induced by cosmic ray strikes [32].…”

Section: Motivationmentioning

confidence: 99%

Efficient software checking for fault tolerance

Garzarán

Snir

2008

2008 IEEE International Symposium on Parallel and Distributed Processing

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As semiconductor technology scales into the deep submicron regime the occurrence of transient or soft errors will increase. This will require new approaches to error detection. Software checking approaches are attractive because they require little hardware modification and can be easily adjusted to fit different reliability and performance requirements. Unfortunately, software checking adds a significant performance overhead.In order to make software checking system more attractive, this dissertation proposes three optimization techniques that reduce the overhead of software error checking approaches. The first technique uses boolean logic to identify code patterns that correspond to outcome tolerant branches. We develop a compiler algorithm that finds those patterns and removes the unnecessary replicas. In the second technique we evaluate the performance benefit obtained by removing address checks before load and stores. In addition, we evaluate the overheads that can be removed when the register file is protected in hardware. The third technique ESoftCheck composes of a set of compiler optimizations to detect and remove "non-vital" checks. ESoftCheck optimizes redundant checks, checks before loop induction variables and invariants and unnecessary checks on platforms where registers are hardware-protected with parity or ECC. ESoftCheck also provides knobs to trade reliability for performance based on the support for recovery and the degree of trustiness of the operations.In the end, this dissertation proposes an interesing future work, which is to find ii a set of variables protecting which it can most likely catch harmful errors that would cause Silent Data Corruption to the program. By ignoring non-harmful errors, the cost spent on detecting them and unnecessary rollbacks can be saved.iii To my husband Yue Zhou and my parents.iv

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Predicting the number of fatal soft errors in Los Alamos national laboratory's ASC Q supercomputer

Cited by 125 publications

References 17 publications

DAFT: Decoupled Acyclic Fault Tolerance

DAFT: Decoupled Acyclic Fault Tolerance

IMCLA: Performance Evaluation of Integrated Multilevel Checkpointing Algorithms using Checkpointing Efficiency

Efficient software checking for fault tolerance

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