Preemptibility-aware responsive multi-core scheduling

Abstract

We propose a novel responsive scheduling technique to minimize the scheduling latency of a real-time process in the multi-core architecture, called the preemptibility-aware scheduling (PAS). Modern complex operating systems contain numerous long interrupt-disabled and non-preemptible sections, and consequently these sections obstruct the immediate handling of urgent interrupts and the rapid scheduling of interruptdriven real-time tasks, causing significant latency between interrupt arrival and process scheduling. The proposed PAS guarantees that before an urgent interrupt occurs, at least one among multiple CPU cores is always in both interruptenabled and preemptible sections, so that the incoming urgent interrupt can always be handled with no significant delay by such CPU core. Experimental results show that the worst-case latency can be reduced by 27-96%.