Preesm: A dataflow-based rapid prototyping framework for simplifying multicore DSP programming

Pelcat, Maxime; Desnos, Karol; Heulot, Julien; Guy, Clément; Nezan, Jean-François; Aridhi, Slaheddine

doi:10.1109/ederc.2014.6924354

Cited by 78 publications

(76 citation statements)

References 8 publications

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“…10 summarizes the experimental setup used to train and test the LSLA MoA of an Exynos 5422 processor from energy measurements. The PREESM dataflow framework [33] is used to generate code for different SDF configurations of a stereo matching application from a Parameterized and Interfaced Synchronous Dataflow (PiSDF) executable specification. PiSDF [34] is an extension to SDF that introduces a hierarchy of composable elements, as well as static and dynamic parameters influencing token production and consumption.…”

Section: B Choosing the Lsla Topologymentioning

confidence: 99%

Reproducible Evaluation of System Efficiency With a Model of Architecture: From Theory to Practice

Pelcat

Mercat

Desnos

et al. 2018

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Current trends in high performance and embedded computing include design of increasingly complex hardware architectures with high parallelism, heterogeneous processing elements and non-uniform communication resources. In order to take hardware and software design decisions, early evaluations of the system non-functional properties are needed. These evaluations of system efficiency require Electronic System-Level (ESL) information on both the algorithms and the architecture.Contrary to algorithm models for which a major body of work has been conducted on defining formal Models of Computation (MoCs), architecture models from the literature are mostly empirical models from which reproducible experimentation requires the accompanying software. In this paper, a precise definition of a Model of Architecture (MoA) is proposed that focuses on reproducibility and abstraction and removes the overlap previously existing between the notions of MoA and MoC. A first MoA, called the Linear System-Level Architecture Model (LSLA), is presented. To demonstrate the generic nature of the proposed new architecture modeling concepts, we show that the LSLA Model can be integrated flexibly with different MoCs.LSLA is then used to model the energy consumption of a State-of-the-Art Multiprocessor System-on-Chip (MPSoC) when running an application described using the Synchronous Dataflow (SDF) MoC. A method to automatically learn LSLA model parameters from platform measurements is introduced. Despite the high complexity of the underlying hardware and software, a simple LSLA model is demonstrated to estimate the energy consumption of the MPSoC with a fidelity of 86%.

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Section: B Choosing the Lsla Topologymentioning

confidence: 99%

Reproducible Evaluation of System Efficiency With a Model of Architecture: From Theory to Practice

Pelcat

Mercat

Desnos

et al. 2018

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Self Cite

View full text Add to dashboard Cite

show abstract

“…Actually, we propose a new approach that takes advantage from UML as high-level modeling language combined with the Modeling and Analysis of Real-Time and Embedded Systems (MARTE) profile [6] and introduces another level that facilitates IP integration, architecture generation and system analysis. This level is based on the System-Level Architecture Model (S-LAM) [7] which conforms to the IP-XACT standard. S-LAM proposes a simple description of MP2SoC architectures at system-level while reducing the architecture simulation complexity.…”

Section: Building Well Structured Methodologiesmentioning

confidence: 99%

“…The generated πSDF graphs of the application, S-LAM description of the architecture and scenario file can be automatically analyzed and processed using the PREESM [7] rapid prototyping tool for automatic allocation, scheduling [16], system performance estimation [7] and finally code generation.…”

Section: Preesm Tool Back-endmentioning

confidence: 99%

“…While links are pointto-point connections between communication interfaces (ComInterface element) of the component instances, hierarchy connections connect sub-designs or components from different hierarchical levels using hierarchy ports. The original Ecore version of the S-LAM meta-model [7] was extended to allow the specification of a repetition of the same IP. The repetitionShape attribute was added to the ComponentInstance meta-class allowing to specify the repetition shape of a given component instance.…”

Section: The Design Meta-model: Supporting Hierarchy and Compositionmentioning

confidence: 99%

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Automatic Generation of S-LAM Descriptions from UML/MARTE for the DSE of Massively Parallel Embedded Systems

Ammar

Baklouti

Pelcat

et al. 2015

Studies in Computational Intelligence

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Massively Parallel Multi-Processors System-on-Chip (MP2SoC) architectures require efficient programming models and tools to deal with the massive parallelism present within the architecture. In this paper, we propose a tool which automates the generation of the System-Level Architecture Model (S-LAM) from a Unified Modeling Language-based (UML) model annotated with the Modeling and Analysis of Real-Time and Embedded Systems (MARTE) profile. The S-LAMbased description of the MP2SoC architecture is conformed to the IP-XACT standard. The integration of our generator within a co-design framework provides the specification of the whole MP2SoC system using UML and MARTE. Then, gradual refinements allow the execution of a rapid prototyping process.

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“…However, all of these tools do not provide accurate results for the processing time, energy consumption and accuracy. The Synopsys Platform Architect, Preesm [9], Imperas Open Virtual Platform (OVP), Intels modeling tool Cofluent Studio and gem5. Tools such as Preesm are strongly limited regarding the choice of hardware architectures.…”

Section: Introductionmentioning

confidence: 99%

A Hybrid Simulation Environment to Estimate the Accuracy, Energy Consumption and Processing Time for Image Processing Applications

Hartmann¹,

Fey²

2017

International Journal of Information and Computer Science

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With increasing complexity in embedded image processing applications the hardware virtualization and emulation of image processing architectures have become an important factor in the design phase of such hardware and software systems. The alternatives to simulation on virtual hardware are tests on real hardware which are expensive, time and resource intensive. For reducing the costs of system evaluation in the early state of projects hardware simulators are created. Nowadays, these simulators are often inaccurate, have long simulation time for complex systems, and do not support non-functional properties such as processing time, power consumption and processing accuracy. In our work we introduce an image processing system simulator combined with a neural network for the estimation of the non-functional properties of image processing applications such as, processing time, energy consumption and processing accuracy.

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Preesm: A dataflow-based rapid prototyping framework for simplifying multicore DSP programming

Cited by 78 publications

References 8 publications

Reproducible Evaluation of System Efficiency With a Model of Architecture: From Theory to Practice

Reproducible Evaluation of System Efficiency With a Model of Architecture: From Theory to Practice

Automatic Generation of S-LAM Descriptions from UML/MARTE for the DSE of Massively Parallel Embedded Systems

A Hybrid Simulation Environment to Estimate the Accuracy, Energy Consumption and Processing Time for Image Processing Applications

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