Preliminary Defect Analysis of 8T SRAM Cells for In-Memory Computing Architectures

Abstract

In-Memory-Computing (IMC) paradigm has been proposed as an alternative to overcome the memory wall faced by conventional von Neumann computing architectures. IMC architectures proposed today are built either from volatile or non-volatile basic memory cells, but a common feature is that all of them are prone to manufacturing defects in the same way as conventional memories. In this paper, we propose to analyze the behavior of an IMC 8T SRAM cell in presence of defects located in the read port of the cell. A model of a basic IMC memory array has been set up to simulate the behavior of the cell in the two modes of operation: memory mode and computing mode. Resistive short defects were injected into the read port and then analyzed. Preliminary results show that these defects can severely impact the behavior of the 8T SRAM in memory mode as well as computing mode. The final goal of this study is to develop effective test algorithms for these defects.

Analysis of resistive defects on a foundry 8T SRAM-based IMC architecture

“…The March C-test algorithm is the following {⇕ (w0); ⇑ (r0, w1); ⇑ (r1, w0); ⇓ (r0, w1); ⇓ (r1, w0); ⇕ (r0)} and has a complexity of 10N (N being the number of cells). It provides a 100% coverage of Stuck-at-Faults (SAF), Transition Faults (TF), idempotent and inversion Coupling Faults (CFid, CFin) and Address decoder Faults (AF), but does not cover all the resistive-short defects located in the read port of the IMC 8T SRAM cells [19]. In summary, functional tests and test algorithms already developed for conventionnel 6T SRAMs testing were used to test 8T SRAM-based computing architectures in memory mode in [17][18].…”

“…These solutions mainly consist in modifying March test algorithms through the addition of computing operations. However, as shown by preliminary results presented in [19], these tests do not cover all potential defects that can occur in the IMC architecture. In particular, defects in the memory read port are not covered.…”

Intra-cell Resistive-Open Defect Analysis on a Foundry 8T SRAM-based IMC Architecture

“…These solutions mainly consist in adding computing operations to the original March test algorithm. As shown in [7], these tests however do not cover all potential defects in the targeted IMC architecture. In particular, defects in the memory read port are not covered.…”

Structured Test Development Approach for Computation-in-Memory Architectures

“…There is only a limited work published on testing of CIM. Several researchers have studied the impact of resistive defects (e.g., an open connection, or a short-circuit to GND) on the performance of a CIM architecture and subsequently developed tests to detect such modeled defects [4,[10][11][12][13]. The work has shown that there are unique computation faults that are not seen in regular memories.…”