PRIMA: Passive Reduced-Order Interconnect Macromodeling Algorithm

Odabasioglu, Altan; Celik, M.; Pileggi, Lawrence T.

doi:10.1007/978-1-4615-0292-0_34

Cited by 64 publications

(126 citation statements)

References 6 publications

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“…The resulting macromodels lack provable error bounds and any guarantee of preserving stability or passivity of the original model. Nonetheless, moment matching algorithms like Padé via Lanczos (PVL [5]), Passive Reduced-order Interconnect Macromodeling Algorithm (PRIMA [17]), and Structure-Preserving Reduced-Order Interconnect Macromodeling (SPRIM [6]) are popular in the electrical engineering community. Truncated Balanced Realization (TBR) methods generate macromodels that have provable error bounds and guaranteed preservation of stability when the dynamical system is linear time-invariant.…”

Section: Model Order Reductionmentioning

confidence: 99%

“…The Passive Reduced-Order Interconnect Macromodeling Algorithm (PRIMA) is proposed by Odabasioglu et al [17] in 1998. The algorithm utilizes the block Arnoldi procedure.…”

Section: Primamentioning

confidence: 99%

“…This constraint will be taken into account during the presentation of the model order reduction schemes. For more details on reduced model integration, the reader is referred to [17] and the references therein.…”

Section: Integrating Reduced Modelsmentioning

confidence: 99%

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Solution methods for very highly integrated circuits.

Nong¹,

Thornquist²,

Chen³

et al. 2010

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While advances in manufacturing enable the fabrication of integrated circuits containing tens-to-hundreds of millions of devices, the time-sensitive modeling and simulation necessary to design these circuits poses a significant computational challenge. This is especially true for mixed-signal integrated circuits where detailed performance analyses are necessary for the individual analog/digital circuit components as well as the full system. When the integrated circuit has millions of devices, performing a full system simulation is practically infeasible using currently available Electrical Design Automation (EDA) tools. The principal reason for this is the time required for the nonlinear solver to compute the solutions of large linearized systems during the simulation of these circuits. The research presented in this report aims to address the computational difficulties introduced by these large linearized systems by using Model Order Reduction (MOR) to (i) generate specialized preconditioners that accelerate the computation of the linear system solution and (ii) reduce the overall dynamical system size. MOR techniques attempt to produce macromodels that capture the desired input-output behavior of larger dynamical systems and enable substantial speedups in simulation time. Several MOR techniques that have been developed under the LDRD on "Solution Methods for Very Highly Integrated Circuits" will be presented in this report. Among those presented are techniques for linear time-invariant dynamical systems that either extend current approaches or improve the time-domain performance of the reduced model using novel error bounds and a new approach for linear time-varying dynamical systems that guarantees dimension reduction, which has not been proven before. Progress on preconditioning power grid systems using multi-grid techniques will be presented as well as a framework for delivering MOR techniques to the user community using Trilinos and the Xyce circuit simulator, both prominent world-class software tools.

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Section: Model Order Reductionmentioning

confidence: 99%

“…The Passive Reduced-Order Interconnect Macromodeling Algorithm (PRIMA) is proposed by Odabasioglu et al [17] in 1998. The algorithm utilizes the block Arnoldi procedure.…”

Section: Primamentioning

confidence: 99%

See 1 more Smart Citation

Solution methods for very highly integrated circuits.

Nong¹,

Thornquist²,

Chen³

et al. 2010

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“…One shortcoming of this model is that it does not include the inductive effects and is a first order moment approximation. Higher order propagation delays can be obtained through moment matching methods such as AWE [3], PRIMA [4], Multi-node Moment Matching [5]. But they are efficient only for handling the tree and tree-like topologies.…”

Section: Introductionmentioning

confidence: 99%

“…We target at very large clock networks from real designs and use a divide-and-conquer scheme to perform the complexity reduction. The resulting algorithm can give faster yet more accurate results for hybrid structured clock network than existing methods [1], [4], [6]. We demonstrated the performance through a comparison with the widely used simulator HSPICE.…”

Section: Introductionmentioning

confidence: 99%

A Fast Delay Computation for the Hybrid Structured Clock Network

Zou

Cai

Zhou

et al. 2005

IEICE Transactions on Fundamentals of Electronics, Communicatio

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Student Member, Yici CAI †b) , Qiang ZHOU †c) , Xianlong HONG †d) , and Sheldon X.-D. TAN † †e) , Nonmembers SUMMARY This paper presents a novel approach to reducing the complexity of the transient linear circuit analysis for a hybrid structured clock network. Topology reduction is first used to reduce the complexity of the circuits and a preconditioned Krylov-subspace iterative method is then used to perform the nodal analysis on the reduced circuits. By proper selection of the simulation time step and interval based on Elmore delays, the delay of the clock signal between the clock source and the sink node as well as the clock skews between the sink nodes can be computed efficiently and accurately. Our experimental results show that the proposed algorithm is two orders of magnitude faster than HSPICE without loss of accuracy and stability. The maximum error is within 0.4% of the exact delay time.

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Spice

Cheng,

Ho,

Holtz

2024

Encyclopedia of RF and Microwave Engineering

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SPICE (Simulation Program with Integrated Circuit Emphasis) is a program for electronic circuit design simulation and is one of the most successful academic products. Integrated circuit (IC) designers often use SPICE to check functionality, integrity, and power integrity before physical implementation (i.e., layout design) and tape‐out. Using SPICE to verify IC designs is essential for circuit validation due to the high cost of photolithographic masks and other manufacturing processes. The input to SPICE is a design “netlist,” which is composed of electronic components, such as resistance, transistor, capacitance, and sources. After the SPICE simulation, users can inspect the signal waveform or perform measurements virtually on the probing nodes in the netlist. Nowadays, there are open‐source and commercial SPICE programs for designers or researchers to incorporate SPICE into their projects. Active electronic components are usually described in the device model to reflect the current and voltage behaviors. According to user requirements, SPICE is capable of performing several types of analysis (e.g., DC, AC, transient, and DC sweep) and provides a bridge between time and frequency domain. Facing future challenges, many emerging methods and algorithms have been proposed to address the growing complexity of circuit designs and performance bottlenecks. Additionally, as technology evolves, SPICE continues to add device models to accurately capture the electronic component behavior in advanced technology nodes, such as the TSMC Interface and the Open Model Interface models.

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PRIMA: Passive Reduced-Order Interconnect Macromodeling Algorithm

Abstract: Abstract

Cited by 64 publications

References 6 publications

Solution methods for very highly integrated circuits.

Solution methods for very highly integrated circuits.

A Fast Delay Computation for the Hybrid Structured Clock Network

Spice

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