2012
DOI: 10.1143/jjap.51.050205
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Primary Factor Extracted for Anomalous Decline of Drain Current in Metal–Oxide–Semiconductor Field-Effect Transistors

Abstract: A statistical approach has been exploratively applied to extract an influential factor of anomalous decreases in drain current observed in metal–oxide–semiconductor field-effect transistors with large channel widths. Since negative slopes were detected in drain current vs drain voltage (I d–V ds) curves even with negligible heat quantity or density, the self-heating effect was excluded as the primary factor. In contrast, the aspect ratio of the device areas showed a signific… Show more

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Cited by 2 publications
(7 citation statements)
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“…The author attempted to generate an acoustic standing wave in the device using impact ionization incorporated with the stimulated emission of phonons. [4][5][6] Being fabricated using only a commercially available CMOS process, the new device preliminarily exhibited a sharp resonance at 300 MHz with a Q factor of over 1500, more than 100 times larger than that of LC resonators.…”
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“…The author attempted to generate an acoustic standing wave in the device using impact ionization incorporated with the stimulated emission of phonons. [4][5][6] Being fabricated using only a commercially available CMOS process, the new device preliminarily exhibited a sharp resonance at 300 MHz with a Q factor of over 1500, more than 100 times larger than that of LC resonators.…”
mentioning
confidence: 99%
“…The structure and fabrication process of the above device are almost the same as those of the n-type MOS transistor described in detail elsewhere. 4,5) The device was fabricated using the CMOS process for 2.5 V transistors with a gate length (L) of 0.3 m and a total channel width W total of 400 m in the double-well structure on a p-type Si substrate with a thickness of 725 m (Fig. 1).…”
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“…13) The structure and fabrication of the MOSFET measured in this study are also described elsewhere. 8,13,14) The 2.5 V n-type MOSFET was fabricated in a double-well structure on a p-type Si substrate using a standard complementary metal-oxide-semiconductor (CMOS) process with the minimum gate length of L ¼ 0:3 m. Placed in a rectangular region surrounded by shallow-trench isolation (STI), multiple gate electrodes (N ¼ 40) with a width of W ¼ 40 m were connected in parallel to provide a total channel width of W total ¼ 1600 m. Four dummy gate electrodes (N dum ¼ 4) were inserted between all active gate electrodes to increase the interelectrode spacing (d ¼ 3:6 m), and connected in parallel to the ground potential in the following measurements. 8,13,14) I sub and I d were simultaneously measured for a device using a semiconductor parameter analyzer (Agilent 4156B) and a power unit (41501B), and plotted on a logarithmic scale as a function of V gs , as shown in Figs.…”
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confidence: 99%