“…13) The structure and fabrication of the MOSFET measured in this study are also described elsewhere. 8,13,14) The 2.5 V n-type MOSFET was fabricated in a double-well structure on a p-type Si substrate using a standard complementary metal-oxide-semiconductor (CMOS) process with the minimum gate length of L ¼ 0:3 m. Placed in a rectangular region surrounded by shallow-trench isolation (STI), multiple gate electrodes (N ¼ 40) with a width of W ¼ 40 m were connected in parallel to provide a total channel width of W total ¼ 1600 m. Four dummy gate electrodes (N dum ¼ 4) were inserted between all active gate electrodes to increase the interelectrode spacing (d ¼ 3:6 m), and connected in parallel to the ground potential in the following measurements. 8,13,14) I sub and I d were simultaneously measured for a device using a semiconductor parameter analyzer (Agilent 4156B) and a power unit (41501B), and plotted on a logarithmic scale as a function of V gs , as shown in Figs.…”